| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AsmBackend.cpp | 408 unsigned Reg1 = MRI.getLLVMRegNum(Inst.getRegister(), true); in generateCompactUnwindEncoding() local
425 Reg1 = getXRegFromWReg(Reg1); in generateCompactUnwindEncoding()
428 if (Reg1 == AArch64::X19 && Reg2 == AArch64::X20 && in generateCompactUnwindEncoding()
431 else if (Reg1 == AArch64::X21 && Reg2 == AArch64::X22 && in generateCompactUnwindEncoding()
434 else if (Reg1 == AArch64::X23 && Reg2 == AArch64::X24 && in generateCompactUnwindEncoding()
437 else if (Reg1 == AArch64::X25 && Reg2 == AArch64::X26 && in generateCompactUnwindEncoding()
440 else if (Reg1 == AArch64::X27 && Reg2 == AArch64::X28 && in generateCompactUnwindEncoding()
444 Reg1 = getDRegFromBReg(Reg1); in generateCompactUnwindEncoding()
451 if (Reg1 == AArch64::D8 && Reg2 == AArch64::D9 && in generateCompactUnwindEncoding()
454 else if (Reg1 == AArch64::D10 && Reg2 == AArch64::D11 && in generateCompactUnwindEncoding()
[all …]
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| /external/llvm/include/llvm/MC/ |
| D | MCRegisterInfo.h | 80 bool contains(unsigned Reg1, unsigned Reg2) const { in contains() argument
81 return contains(Reg1) && contains(Reg2); in contains()
525 uint16_t Reg1; variable
527 MCRegUnitRootIterator() : Reg0(0), Reg1(0) {} in MCRegUnitRootIterator()
531 Reg1 = MCRI->RegUnitRoots[RegUnit][1]; in MCRegUnitRootIterator()
547 Reg0 = Reg1;
548 Reg1 = 0;
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64FrameLowering.cpp | 630 unsigned Reg1 = CSI[idx].getReg(); in spillCalleeSavedRegisters() local
652 if (AArch64::GPR64RegClass.contains(Reg1)) { in spillCalleeSavedRegisters()
660 } else if (AArch64::FPR64RegClass.contains(Reg1)) { in spillCalleeSavedRegisters()
670 DEBUG(dbgs() << "CSR spill: (" << TRI->getName(Reg1) << ", " in spillCalleeSavedRegisters()
683 .addReg(Reg1, getPrologueDeath(MF, Reg1)) in spillCalleeSavedRegisters()
705 unsigned Reg1 = CSI[i].getReg(); in restoreCalleeSavedRegisters() local
723 if (AArch64::GPR64RegClass.contains(Reg1)) { in restoreCalleeSavedRegisters()
730 } else if (AArch64::FPR64RegClass.contains(Reg1)) { in restoreCalleeSavedRegisters()
739 DEBUG(dbgs() << "CSR restore: (" << TRI->getName(Reg1) << ", " in restoreCalleeSavedRegisters()
753 .addReg(Reg1, getDefRegState(true)) in restoreCalleeSavedRegisters()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsAsmPrinter.h | 67 void EmitInstrRegReg(unsigned Opcode, unsigned Reg1, unsigned Reg2);
69 void EmitInstrRegRegReg(unsigned Opcode, unsigned Reg1, unsigned Reg2,
72 void EmitMovFPIntPair(unsigned MovOpc, unsigned Reg1, unsigned Reg2,
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| D | MipsAsmPrinter.cpp | 731 void MipsAsmPrinter::EmitInstrRegReg(unsigned Opcode, unsigned Reg1, in EmitInstrRegReg() argument
740 unsigned Temp = Reg1; in EmitInstrRegReg()
741 Reg1 = Reg2; in EmitInstrRegReg()
745 I.addOperand(MCOperand::CreateReg(Reg1)); in EmitInstrRegReg()
750 void MipsAsmPrinter::EmitInstrRegRegReg(unsigned Opcode, unsigned Reg1, in EmitInstrRegRegReg() argument
754 I.addOperand(MCOperand::CreateReg(Reg1)); in EmitInstrRegRegReg()
760 void MipsAsmPrinter::EmitMovFPIntPair(unsigned MovOpc, unsigned Reg1, in EmitMovFPIntPair() argument
764 unsigned temp = Reg1; in EmitMovFPIntPair()
765 Reg1 = Reg2; in EmitMovFPIntPair()
768 EmitInstrRegReg(MovOpc, Reg1, FPReg1); in EmitMovFPIntPair()
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| D | Mips16InstrInfo.cpp | 266 unsigned Reg1, unsigned Reg2) const { in adjustStackPtrBig() argument
278 MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::LwConstant32), Reg1); in adjustStackPtrBig()
282 MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::AdduRxRyRz16), Reg1); in adjustStackPtrBig()
283 MIB3.addReg(Reg1); in adjustStackPtrBig()
287 MIB4.addReg(Reg1, RegState::Kill); in adjustStackPtrBig()
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| D | Mips16InstrInfo.h | 117 unsigned Reg1, unsigned Reg2) const;
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| D | MipsSEFrameLowering.cpp | 331 unsigned Reg1 = in emitPrologue() local
335 std::swap(Reg0, Reg1); in emitPrologue()
343 MCCFIInstruction::createOffset(nullptr, Reg1, Offset + 4)); in emitPrologue()
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrBuilder.h | 116 unsigned Reg1, bool isKill1, in addRegReg() argument
118 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1) in addRegReg()
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| /external/llvm/lib/CodeGen/ |
| D | AggressiveAntiDepBreaker.h | 104 unsigned UnionGroups(unsigned Reg1, unsigned Reg2);
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| D | TargetInstrInfo.cpp | 137 unsigned Reg1 = MI->getOperand(Idx1).getReg(); in commuteInstruction() local
146 if (HasDef && Reg0 == Reg1 && in commuteInstruction()
154 Reg0 = Reg1; in commuteInstruction()
168 MI->getOperand(Idx2).setReg(Reg1); in commuteInstruction()
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| D | AggressiveAntiDepBreaker.cpp | 80 unsigned AggressiveAntiDepState::UnionGroups(unsigned Reg1, unsigned Reg2) in UnionGroups() argument
86 unsigned Group1 = GetGroup(Reg1); in UnionGroups()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCRegisterInfo.cpp | 415 unsigned Reg1 = Reg; in lowerCRSpilling() local
420 .addReg(Reg1, RegState::Kill) in lowerCRSpilling()
459 unsigned Reg1 = Reg; in lowerCRRestore() local
465 .addReg(Reg1, RegState::Kill).addImm(32-ShiftBits).addImm(0) in lowerCRRestore()
533 unsigned Reg1 = Reg; in lowerCRBitSpilling() local
538 .addReg(Reg1, RegState::Kill) in lowerCRBitSpilling()
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| D | PPCInstrInfo.cpp | 251 unsigned Reg1 = MI->getOperand(1).getReg(); in commuteInstruction() local
260 if (Reg0 == Reg1) { in commuteInstruction()
280 .addReg(Reg1, getKillRegState(Reg1IsKill)) in commuteInstruction()
289 MI->getOperand(2).setReg(Reg1); in commuteInstruction()
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| /external/llvm/lib/Target/ARM/InstPrinter/ |
| D | ARMInstPrinter.cpp | 1322 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1); in printVectorListTwo() local
1326 printRegName(O, Reg1); in printVectorListTwo()
1335 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2); in printVectorListTwoSpaced() local
1339 printRegName(O, Reg1); in printVectorListTwoSpaced()
1386 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1); in printVectorListTwoAllLanes() local
1390 printRegName(O, Reg1); in printVectorListTwoAllLanes()
1431 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2); in printVectorListTwoSpacedAllLanes() local
1435 printRegName(O, Reg1); in printVectorListTwoSpacedAllLanes()
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| /external/llvm/include/llvm/Target/ |
| D | TargetRegisterInfo.h | 81 bool contains(unsigned Reg1, unsigned Reg2) const { in contains() argument
82 return MC->contains(Reg1, Reg2); in contains()
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| /external/llvm/lib/Target/ARM/ |
| D | A15SDOptimizer.cpp | 84 unsigned Reg1, unsigned Reg2);
464 unsigned Reg1, unsigned Reg2) { in createRegSequence() argument
470 .addReg(Reg1) in createRegSequence()
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| D | Thumb2SizeReduction.cpp | 642 unsigned Reg1 = MI->getOperand(1).getReg(); in ReduceTo2Addr() local
647 if (!isARMLowRegister(Reg0) || !isARMLowRegister(Reg1) in ReduceTo2Addr()
653 if (Reg1 != Reg0) in ReduceTo2Addr()
660 } else if (Reg0 != Reg1) { in ReduceTo2Addr()
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| D | ARMFastISel.cpp | 2779 unsigned Reg1 = getRegForValue(Src1Value); in SelectShift() local
2780 if (Reg1 == 0) return false; in SelectShift()
2793 .addReg(Reg1); in SelectShift()
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| D | ARMISelDAGToDAG.cpp | 3366 unsigned Reg1 = cast<RegisterSDNode>(V1)->getReg(); in SelectInlineAsm() local
3390 SDValue T1 = CurDAG->getCopyToReg(Sub1, dl, Reg1, Sub1, T0.getValue(1)); in SelectInlineAsm()
3406 SDValue T1 = CurDAG->getCopyFromReg(Chain, dl, Reg1, MVT::i32, in SelectInlineAsm()
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| D | ARMBaseInstrInfo.cpp | 2590 unsigned Reg1 = UseMI->getOperand(OpIdx).getReg(); in FoldImmediate() local
2596 .addReg(Reg1, getKillRegState(isKill)) in FoldImmediate()
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| /external/llvm/utils/TableGen/ |
| D | CodeGenRegisters.cpp | 1128 CodeGenRegister *Reg1 = Registers[i]; in computeComposites() local
1131 if (TopoSigs.test(Reg1->getTopoSig())) in computeComposites()
1133 TopoSigs.set(Reg1->getTopoSig()); in computeComposites()
1135 const CodeGenRegister::SubRegMap &SRM1 = Reg1->getSubRegs(); in computeComposites()
1141 if (Reg1 == Reg2) in computeComposites()
1153 CodeGenSubRegIndex *Idx3 = Reg1->getSubRegIndex(Reg3); in computeComposites()
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| /external/llvm/lib/MC/ |
| D | MCDwarf.cpp | 1091 unsigned Reg1 = Instr.getRegister(); in EmitCFIInstruction() local
1095 Streamer.AddComment(Twine("Reg1 ") + Twine(Reg1)); in EmitCFIInstruction()
1099 Streamer.EmitULEB128IntValue(Reg1); in EmitCFIInstruction()
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| /external/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 5529 unsigned Reg1 = Op1.getReg(); in ParseInstruction() local
5531 unsigned Rt = MRI->getEncodingValue(Reg1); in ParseInstruction()
5541 unsigned NewReg = MRI->getMatchingSuperReg(Reg1, ARM::gsub_0, in ParseInstruction()
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