| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AsmBackend.cpp | 415 unsigned Reg2 = MRI.getLLVMRegNum(Inst2.getRegister(), true); in generateCompactUnwindEncoding() local
426 Reg2 = getXRegFromWReg(Reg2); in generateCompactUnwindEncoding()
428 if (Reg1 == AArch64::X19 && Reg2 == AArch64::X20 && in generateCompactUnwindEncoding()
431 else if (Reg1 == AArch64::X21 && Reg2 == AArch64::X22 && in generateCompactUnwindEncoding()
434 else if (Reg1 == AArch64::X23 && Reg2 == AArch64::X24 && in generateCompactUnwindEncoding()
437 else if (Reg1 == AArch64::X25 && Reg2 == AArch64::X26 && in generateCompactUnwindEncoding()
440 else if (Reg1 == AArch64::X27 && Reg2 == AArch64::X28 && in generateCompactUnwindEncoding()
445 Reg2 = getDRegFromBReg(Reg2); in generateCompactUnwindEncoding()
451 if (Reg1 == AArch64::D8 && Reg2 == AArch64::D9 && in generateCompactUnwindEncoding()
454 else if (Reg1 == AArch64::D10 && Reg2 == AArch64::D11 && in generateCompactUnwindEncoding()
[all …]
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64FrameLowering.cpp | 631 unsigned Reg2 = CSI[idx + 1].getReg(); in spillCalleeSavedRegisters() local
653 assert(AArch64::GPR64RegClass.contains(Reg2) && in spillCalleeSavedRegisters()
661 assert(AArch64::FPR64RegClass.contains(Reg2) && in spillCalleeSavedRegisters()
671 << TRI->getName(Reg2) << ") -> fi#(" << CSI[idx].getFrameIdx() in spillCalleeSavedRegisters()
682 MIB.addReg(Reg2, getPrologueDeath(MF, Reg2)) in spillCalleeSavedRegisters()
706 unsigned Reg2 = CSI[i + 1].getReg(); in restoreCalleeSavedRegisters() local
724 assert(AArch64::GPR64RegClass.contains(Reg2) && in restoreCalleeSavedRegisters()
731 assert(AArch64::FPR64RegClass.contains(Reg2) && in restoreCalleeSavedRegisters()
740 << TRI->getName(Reg2) << ") -> fi#(" << CSI[i].getFrameIdx() in restoreCalleeSavedRegisters()
752 MIB.addReg(Reg2, getDefRegState(true)) in restoreCalleeSavedRegisters()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsAsmPrinter.h | 67 void EmitInstrRegReg(unsigned Opcode, unsigned Reg1, unsigned Reg2);
69 void EmitInstrRegRegReg(unsigned Opcode, unsigned Reg1, unsigned Reg2,
72 void EmitMovFPIntPair(unsigned MovOpc, unsigned Reg1, unsigned Reg2,
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| D | MipsAsmPrinter.cpp | 732 unsigned Reg2) { in EmitInstrRegReg() argument
741 Reg1 = Reg2; in EmitInstrRegReg()
742 Reg2 = Temp; in EmitInstrRegReg()
746 I.addOperand(MCOperand::CreateReg(Reg2)); in EmitInstrRegReg()
751 unsigned Reg2, unsigned Reg3) { in EmitInstrRegRegReg() argument
755 I.addOperand(MCOperand::CreateReg(Reg2)); in EmitInstrRegRegReg()
761 unsigned Reg2, unsigned FPReg1, in EmitMovFPIntPair() argument
765 Reg1 = Reg2; in EmitMovFPIntPair()
766 Reg2 = temp; in EmitMovFPIntPair()
769 EmitInstrRegReg(MovOpc, Reg2, FPReg2); in EmitMovFPIntPair()
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| D | Mips16InstrInfo.h | 117 unsigned Reg1, unsigned Reg2) const;
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| D | Mips16InstrInfo.cpp | 266 unsigned Reg1, unsigned Reg2) const { in adjustStackPtrBig()
280 MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::MoveR3216), Reg2); in adjustStackPtrBig()
284 MIB3.addReg(Reg2, RegState::Kill); in adjustStackPtrBig()
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| D | MipsISelLowering.cpp | 2268 unsigned Reg2 = State.AllocateReg(IntRegs, IntRegsSize); in CC_MipsO32() local
2269 if (Reg2 == Mips::A1 || Reg2 == Mips::A3) in CC_MipsO32()
2728 unsigned Reg2 = addLiveIn(DAG.getMachineFunction(), in LowerFormalArguments() local
2730 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, DL, Reg2, RegVT); in LowerFormalArguments()
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| /external/llvm/test/CodeGen/Hexagon/ |
| D | newvaluejump2.ll | 9 %Reg2 = alloca i8, align 1
10 %0 = load i8* %Reg2, align 1
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrBuilder.h | 117 unsigned Reg2, bool isKill2) { in addRegReg() argument
119 .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0); in addRegReg()
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| /external/llvm/include/llvm/MC/ |
| D | MCRegisterInfo.h | 80 bool contains(unsigned Reg1, unsigned Reg2) const { in contains() argument
81 return contains(Reg1) && contains(Reg2); in contains()
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| /external/llvm/lib/CodeGen/ |
| D | AggressiveAntiDepBreaker.h | 104 unsigned UnionGroups(unsigned Reg1, unsigned Reg2);
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| D | TargetInstrInfo.cpp | 138 unsigned Reg2 = MI->getOperand(Idx2).getReg(); in commuteInstruction() local
149 Reg0 = Reg2; in commuteInstruction()
151 } else if (HasDef && Reg0 == Reg2 && in commuteInstruction()
169 MI->getOperand(Idx1).setReg(Reg2); in commuteInstruction()
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| D | AggressiveAntiDepBreaker.cpp | 80 unsigned AggressiveAntiDepState::UnionGroups(unsigned Reg1, unsigned Reg2) in UnionGroups() argument
87 unsigned Group2 = GetGroup(Reg2); in UnionGroups()
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| /external/llvm/lib/Target/ARM/ |
| D | Thumb2SizeReduction.cpp | 645 unsigned Reg2 = MI->getOperand(2).getReg(); in ReduceTo2Addr() local
648 || !isARMLowRegister(Reg2)) in ReduceTo2Addr()
650 if (Reg0 != Reg2) { in ReduceTo2Addr()
678 unsigned Reg2 = MI->getOperand(2).getReg(); in ReduceTo2Addr() local
679 if (Entry.LowRegs2 && !isARMLowRegister(Reg2)) in ReduceTo2Addr()
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| D | A15SDOptimizer.cpp | 84 unsigned Reg1, unsigned Reg2);
464 unsigned Reg1, unsigned Reg2) { in createRegSequence() argument
472 .addReg(Reg2) in createRegSequence()
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| D | ARMFastISel.cpp | 2782 unsigned Reg2 = 0; in SelectShift() local
2784 Reg2 = getRegForValue(Src2Value); in SelectShift()
2785 if (Reg2 == 0) return false; in SelectShift()
2798 MIB.addReg(Reg2); in SelectShift()
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| /external/llvm/include/llvm/Target/ |
| D | TargetRegisterInfo.h | 81 bool contains(unsigned Reg1, unsigned Reg2) const { in contains() argument
82 return MC->contains(Reg1, Reg2); in contains()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.cpp | 252 unsigned Reg2 = MI->getOperand(2).getReg(); in commuteInstruction() local
275 unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg(); in commuteInstruction()
279 .addReg(Reg2, getKillRegState(Reg2IsKill)) in commuteInstruction()
286 MI->getOperand(0).setReg(Reg2); in commuteInstruction()
290 MI->getOperand(1).setReg(Reg2); in commuteInstruction()
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| /external/llvm/lib/MC/ |
| D | MCDwarf.cpp | 1092 unsigned Reg2 = Instr.getRegister2(); in EmitCFIInstruction() local
1096 Streamer.AddComment(Twine("Reg2 ") + Twine(Reg2)); in EmitCFIInstruction()
1100 Streamer.EmitULEB128IntValue(Reg2); in EmitCFIInstruction()
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| /external/llvm/utils/TableGen/ |
| D | CodeGenRegisters.cpp | 1139 CodeGenRegister *Reg2 = i1->second; in computeComposites() local
1141 if (Reg1 == Reg2) in computeComposites()
1143 const CodeGenRegister::SubRegMap &SRM2 = Reg2->getSubRegs(); in computeComposites()
1150 if (Reg2 == Reg3) in computeComposites()
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| /external/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 5530 unsigned Reg2 = Op2.getReg(); in ParseInstruction() local
5532 unsigned Rt2 = MRI->getEncodingValue(Reg2); in ParseInstruction()
|