| /external/llvm/lib/Target/ARM/ |
| D | ARMTargetTransformInfo.cpp | 516 { ISD::SREM, MVT::v1i64, 1 * FunctionCallDivCost}, in getArithmeticInstrCost()
520 { ISD::SREM, MVT::v2i32, 2 * FunctionCallDivCost}, in getArithmeticInstrCost()
524 { ISD::SREM, MVT::v4i16, 4 * FunctionCallDivCost}, in getArithmeticInstrCost()
528 { ISD::SREM, MVT::v8i8, 8 * FunctionCallDivCost}, in getArithmeticInstrCost()
533 { ISD::SREM, MVT::v2i64, 2 * FunctionCallDivCost}, in getArithmeticInstrCost()
537 { ISD::SREM, MVT::v4i32, 4 * FunctionCallDivCost}, in getArithmeticInstrCost()
541 { ISD::SREM, MVT::v8i16, 8 * FunctionCallDivCost}, in getArithmeticInstrCost()
545 { ISD::SREM, MVT::v16i8, 16 * FunctionCallDivCost}, in getArithmeticInstrCost()
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| D | AMDILISelLowering.cpp | 119 setOperationAction(ISD::SREM, VT, Expand); in InitAMDILLowering()
179 setOperationAction(ISD::SREM, MVT::v2i64, Expand); in InitAMDILLowering()
655 LHS = DAG.getNode(ISD::SREM, DL, INTTY, LHS, RHS); in LowerSREM8()
673 LHS = DAG.getNode(ISD::SREM, DL, INTTY, LHS, RHS); in LowerSREM16()
|
| D | AMDGPUISelLowering.cpp | 90 case ISD::SREM: return LowerSREM(Op, DAG); in LowerOperation()
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | AMDILISelLowering.cpp | 119 setOperationAction(ISD::SREM, VT, Expand); in InitAMDILLowering()
179 setOperationAction(ISD::SREM, MVT::v2i64, Expand); in InitAMDILLowering()
655 LHS = DAG.getNode(ISD::SREM, DL, INTTY, LHS, RHS); in LowerSREM8()
673 LHS = DAG.getNode(ISD::SREM, DL, INTTY, LHS, RHS); in LowerSREM16()
|
| D | AMDGPUISelLowering.cpp | 90 case ISD::SREM: return LowerSREM(Op, DAG); in LowerOperation()
|
| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 181 ADD, SUB, MUL, SDIV, UDIV, SREM, UREM, enumerator
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1088 setOperationAction(ISD::SREM, MVT::i32, Expand); in HexagonTargetLowering()
1093 setOperationAction(ISD::SREM, MVT::i64, Expand); in HexagonTargetLowering()
1290 setOperationAction(ISD::SREM, MVT::i32, Expand); in HexagonTargetLowering()
1323 setOperationAction(ISD::SREM, MVT::i32, Expand); in HexagonTargetLowering()
1326 setOperationAction(ISD::SREM, MVT::i64, Expand); in HexagonTargetLowering()
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGBuilder.h | 704 void visitSRem(const User &I) { visitBinary(I, ISD::SREM); } in visitSRem()
|
| D | SelectionDAGDumper.cpp | 168 case ISD::SREM: return "srem"; in getOperationName()
|
| D | LegalizeVectorOps.cpp | 243 case ISD::SREM: in LegalizeOp()
|
| D | LegalizeVectorTypes.cpp | 115 case ISD::SREM: in ScalarizeVectorResult()
641 case ISD::SREM: in SplitVectorResult()
1590 case ISD::SREM: in WidenVectorResult()
|
| D | SelectionDAG.cpp | 2281 case ISD::SREM: in computeKnownBits()
3019 case ISD::SREM: in FoldConstantArithmetic()
3126 case ISD::SREM: in getNode()
3449 case ISD::SREM: in getNode()
3477 case ISD::SREM: in getNode()
|
| D | FastISel.cpp | 1117 return SelectBinaryOp(I, ISD::SREM); in SelectOperator()
|
| D | LegalizeDAG.cpp | 2199 OtherOpcode = isDIV ? ISD::SREM : ISD::SDIV; in useDivRem()
3607 case ISD::SREM: { in ExpandNode()
3609 bool isSigned = Node->getOpcode() == ISD::SREM; in ExpandNode()
|
| D | LegalizeIntegerTypes.cpp | 112 case ISD::SREM: Res = PromoteIntRes_SDIV(N); break; in PromoteIntegerResult()
1148 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break; in ExpandIntegerResult()
|
| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 156 setOperationAction(ISD::SREM, MVT::i8, Expand); in MSP430TargetLowering()
162 setOperationAction(ISD::SREM, MVT::i16, Expand); in MSP430TargetLowering()
|
| /external/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 860 case ISD::SREM: in canOpTrap()
1352 case SRem: return ISD::SREM; in InstructionOpcodeToISD()
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsSEISelLowering.cpp | 170 setOperationAction(ISD::SREM, MVT::i32, Legal); in MipsSETargetLowering()
215 setOperationAction(ISD::SREM, MVT::i64, Legal); in MipsSETargetLowering()
264 setOperationAction(ISD::SREM, Ty, Legal); in addMSAIntType()
1999 return DAG.getNode(ISD::SREM, DL, Op->getValueType(0), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
|
| D | MipsISelLowering.cpp | 282 setOperationAction(ISD::SREM, MVT::i32, Expand); in MipsTargetLowering()
286 setOperationAction(ISD::SREM, MVT::i64, Expand); in MipsTargetLowering()
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64FastISel.cpp | 1858 case ISD::SREM: in SelectRem()
1966 return SelectRem(I, ISD::SREM); in TargetSelectInstruction()
|
| D | AArch64ISelLowering.cpp | 251 setOperationAction(ISD::SREM, MVT::i32, Expand); in AArch64TargetLowering()
252 setOperationAction(ISD::SREM, MVT::i64, Expand); in AArch64TargetLowering()
534 setOperationAction(ISD::SREM, VT.getSimpleVT(), Expand); in addTypeForNEON()
|
| /external/llvm/lib/Target/R600/ |
| D | AMDGPUISelLowering.cpp | 247 setOperationAction(ISD::SREM, VT, Expand); in AMDGPUTargetLowering()
306 setOperationAction(ISD::SREM, VT, Expand); in AMDGPUTargetLowering()
535 case ISD::SREM: return LowerSREM(Op, DAG); in LowerOperation()
|
| D | R600ISelLowering.cpp | 163 setOperationAction(ISD::SREM, MVT::i64, Custom); in R600TargetLowering()
871 case ISD::SREM: { in ReplaceNodeResults()
|
| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 1405 setOperationAction(ISD::SREM, MVT::i32, Expand); in SparcTargetLowering()
1412 setOperationAction(ISD::SREM, MVT::i64, Expand); in SparcTargetLowering()
|
| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 326 def srem : SDNode<"ISD::SREM" , SDTIntBinOp>;
|