| /external/llvm/utils/TableGen/ |
| D | CodeGenSchedule.cpp | 408 const CodeGenSchedRW &SchedRW = getSchedRW(RWIdx, IsRead); in expandRWSequence() local
409 if (!SchedRW.IsSequence) { in expandRWSequence()
414 SchedRW.TheDef ? SchedRW.TheDef->getValueAsInt("Repeat") : 1; in expandRWSequence()
416 for (IdxIter I = SchedRW.Sequence.begin(), E = SchedRW.Sequence.end(); in expandRWSequence()
490 CodeGenSchedRW SchedRW(RWIdx, IsRead, Seq, genRWName(Seq, IsRead)); in findOrInsertRW() local
492 SchedReads.push_back(SchedRW); in findOrInsertRW()
494 SchedWrites.push_back(SchedRW); in findOrInsertRW()
967 const CodeGenSchedRW &SchedRW, unsigned TransIdx,
990 const CodeGenSchedRW &SchedRW = SchedModels.getSchedRW(I->RWIdx, I->IsRead); in mutuallyExclusive() local
991 assert(SchedRW.HasVariants && "PredCheck must refer to a SchedVariant"); in mutuallyExclusive()
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrSystem.td | 16 let SchedRW = [WriteSystem] in {
39 } // SchedRW
48 let SchedRW = [WriteSystem] in {
72 } // SchedRW
78 let SchedRW = [WriteSystem] in {
119 } // SchedRW
124 let SchedRW = [WriteSystem] in {
138 } // SchedRW
143 let SchedRW = [WriteSystem] in {
157 } // SchedRW
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| D | X86InstrFPStack.td | 216 let SchedRW = [WriteFAddLd] in {
221 let SchedRW = [WriteFMulLd] in {
224 let SchedRW = [WriteFDivLd] in {
240 let SchedRW = [WriteFAdd] in {
250 } // SchedRW
251 let SchedRW = [WriteFMul] in {
255 } // SchedRW
256 let SchedRW = [WriteFDiv] in {
263 } // SchedRW
282 let SchedRW = [WriteFSqrt] in {
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| D | X86InstrInfo.td | 912 let neverHasSideEffects = 1, SchedRW = [WriteZero] in {
925 let SchedRW = [WriteALU] in {
935 } // SchedRW
942 let mayLoad = 1, SchedRW = [WriteLoad] in {
960 } // mayLoad, SchedRW
962 let mayStore = 1, SchedRW = [WriteStore] in {
994 } // mayStore, SchedRW
998 let mayLoad = 1, SchedRW = [WriteLoad] in {
1005 } // mayLoad, SchedRW
1006 let mayStore = 1, SchedRW = [WriteStore] in {
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| D | X86InstrArithmetic.td | 17 let SchedRW = [WriteLEA] in {
39 } // SchedRW
154 let isCommutable = 1, SchedRW = [WriteIMul] in {
173 } // isCommutable, SchedRW
176 let SchedRW = [WriteIMulLd, ReadAfterLd] in {
198 } // SchedRW
205 let SchedRW = [WriteIMul] in {
243 } // SchedRW
246 let SchedRW = [WriteIMulLd] in {
288 } // SchedRW
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| D | X86InstrShiftRotate.td | 18 let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
66 } // Constraints = "$src = $dst", SchedRW
69 let SchedRW = [WriteShiftLd, WriteRMW] in {
122 } // SchedRW
124 let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
168 } // Constraints = "$src = $dst", SchedRW
171 let SchedRW = [WriteShiftLd, WriteRMW] in {
222 } // SchedRW
224 let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
279 } // Constraints = "$src = $dst", SchedRW
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| D | X86InstrControl.td | 23 hasCtrlDep = 1, FPForm = SpecialFP, SchedRW = [WriteJumpLd] in {
59 let isBarrier = 1, isBranch = 1, isTerminator = 1, SchedRW = [WriteJump] in {
71 let isBranch = 1, isTerminator = 1, Uses = [EFLAGS], SchedRW = [WriteJump] in {
103 let isBranch = 1, isTerminator = 1, hasSideEffects = 0, SchedRW = [WriteJump] in {
170 let SchedRW = [WriteJump] in {
231 isCodeGenOnly = 1, SchedRW = [WriteJumpLd] in
262 let isCall = 1, Uses = [RSP], SchedRW = [WriteJump] in {
296 SchedRW = [WriteJump] in {
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| D | X86InstrMMX.td | 247 let SchedRW = [WriteMove] in {
262 } // SchedRW
264 let SchedRW = [WriteLoad] in {
270 } // SchedRW
271 let SchedRW = [WriteStore] in
277 let SchedRW = [WriteMove] in {
303 } // SchedRW
598 let SchedRW = [WriteShuffle] in {
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| D | X86ScheduleSLM.td | 58 multiclass SMWriteResPair<X86FoldableSchedWrite SchedRW,
62 def : WriteRes<SchedRW, [ExePort]> { let Latency = Lat; }
66 def : WriteRes<SchedRW.Folded, [MEC_RSV, ExePort]> {
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| D | X86SchedSandyBridge.td | 72 multiclass SBWriteResPair<X86FoldableSchedWrite SchedRW,
76 def : WriteRes<SchedRW, [ExePort]> { let Latency = Lat; }
80 def : WriteRes<SchedRW.Folded, [SBPort23, ExePort]> {
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| D | X86SchedHaswell.td | 78 multiclass HWWriteResPair<X86FoldableSchedWrite SchedRW,
82 def : WriteRes<SchedRW, [ExePort]> { let Latency = Lat; }
86 def : WriteRes<SchedRW.Folded, [HWPort23, ExePort]> {
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| D | X86InstrCMovSetCC.td | 19 isCommutable = 1, SchedRW = [WriteALU] in {
41 SchedRW = [WriteALULd, ReadAfterLd] in {
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| D | X86InstrCompiler.td | 154 let SchedRW = [WriteSystem] in {
192 } // SchedRW
274 let Uses = [EFLAGS], Defs = [EFLAGS], isPseudo = 1, SchedRW = [WriteALU] in {
337 let SchedRW = [WriteMicrocoded] in {
400 } // SchedRW
551 SchedRW = [WriteALULd, WriteRMW] in {
639 SchedRW = [WriteALULd, WriteRMW] in {
673 let isCodeGenOnly = 1, SchedRW = [WriteALULd, WriteRMW] in {
694 SchedRW = [WriteALULd, WriteRMW] in {
701 Predicates = [HasCmpxchg16b], SchedRW = [WriteALULd, WriteRMW] in {
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| D | X86InstrSSE.td | 447 isPseudo = 1, SchedRW = [WriteZero] in {
464 isPseudo = 1, SchedRW = [WriteZero] in {
481 isPseudo = 1, Predicates = [HasAVX], SchedRW = [WriteZero] in {
519 isPseudo = 1, SchedRW = [WriteZero] in {
895 let SchedRW = [WriteStore] in {
928 } // SchedRW
932 SchedRW = [WriteFShuffle] in {
988 let SchedRW = [WriteStore] in {
1005 } // SchedRW
1009 SchedRW = [WriteMove] in {
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| D | X86InstrAVX512.td | 1894 let AddedComplexity = 400, SchedRW = [WriteStore] in {
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| /external/llvm/include/llvm/Target/ |
| D | TargetSchedule.td | 92 // that have a scheduling class (itinerary class or SchedRW list)
202 list<SchedReadWrite> SchedRW = schedrw;
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| D | Target.td | 421 list<SchedReadWrite> SchedRW;
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 2346 let SchedRW = [WriteFDiv] in {
2355 let SchedRW = [WriteFDiv] in {
2362 let SchedRW = [WriteFMul] in {
|