| /external/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 194 unsigned ShiftAmount; member
333 return ShiftedImm.ShiftAmount; in getShiftedImmShift()
662 unsigned Shift = ShiftedImm.ShiftAmount; in isAddSubImm()
1629 unsigned ShiftAmount, in CreateShiftedImm() argument
1634 Op->ShiftedImm.ShiftAmount = ShiftAmount; in CreateShiftedImm()
2172 uint64_t ShiftAmount = 0; in tryParseAddSubImm() local
2178 ShiftAmount = 12; in tryParseAddSubImm()
2182 Operands.push_back(AArch64Operand::CreateShiftedImm(Imm, ShiftAmount, S, E, in tryParseAddSubImm()
2209 int64_t ShiftAmount = Parser.getTok().getIntVal(); in tryParseAddSubImm() local
2211 if (ShiftAmount < 0) { in tryParseAddSubImm()
[all …]
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 636 static bool Is_PostInc_S4_Offset(SDNode * S, int ShiftAmount) { in Is_PostInc_S4_Offset() argument
643 if (ShiftAmount > 0) { in Is_PostInc_S4_Offset()
644 m = v % ShiftAmount; in Is_PostInc_S4_Offset()
645 v = v >> ShiftAmount; in Is_PostInc_S4_Offset()
679 int ShiftAmount = VT.getSizeInBits() / 16; in getPostIndexedAddressParts() local
680 if (isLegal && Is_PostInc_S4_Offset(Offset.getNode(), ShiftAmount)) { in getPostIndexedAddressParts()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorOps.cpp | 780 SDValue ShiftAmount = DAG.getConstant(EltWidth - SrcEltWidth, VT); in ExpandSIGN_EXTEND_VECTOR_INREG() local
782 DAG.getNode(ISD::SHL, DL, VT, Op, ShiftAmount), in ExpandSIGN_EXTEND_VECTOR_INREG()
783 ShiftAmount); in ExpandSIGN_EXTEND_VECTOR_INREG()
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| D | LegalizeDAG.cpp | 403 SDValue ShiftAmount = DAG.getConstant(NumBits, in ExpandUnalignedStore() local
406 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount); in ExpandUnalignedStore()
563 SDValue ShiftAmount = DAG.getConstant(NumBits, in ExpandUnalignedLoad() local
565 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount); in ExpandUnalignedLoad()
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 760 uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue(); in LowerShifts() local
767 if (Opc == ISD::SRL && ShiftAmount) { in LowerShifts()
771 ShiftAmount -= 1; in LowerShifts()
774 while (ShiftAmount--) in LowerShifts()
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| /external/llvm/lib/Analysis/ |
| D | InstructionSimplify.cpp | 1976 unsigned ShiftAmount = Width - 1; in SimplifyICmpInst() local
1978 ShiftAmount = CI2->getValue().countTrailingZeros(); in SimplifyICmpInst()
1979 Lower = CI2->getValue().lshr(ShiftAmount); in SimplifyICmpInst()
1990 unsigned ShiftAmount = Width - 1; in SimplifyICmpInst() local
1992 ShiftAmount = CI2->getValue().countTrailingZeros(); in SimplifyICmpInst()
1996 Upper = CI2->getValue().ashr(ShiftAmount) + 1; in SimplifyICmpInst()
1999 Lower = CI2->getValue().ashr(ShiftAmount); in SimplifyICmpInst()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 6455 static bool findEXTRHalf(SDValue N, SDValue &Src, uint32_t &ShiftAmount, in findEXTRHalf() argument
6467 ShiftAmount = N->getConstantOperandVal(1); in findEXTRHalf()
7026 int64_t ShiftAmount; in tryCombineShiftImm() local
7036 ShiftAmount = SplatValue.getSExtValue(); in tryCombineShiftImm()
7038 ShiftAmount = CVN->getSExtValue(); in tryCombineShiftImm()
7069 if (IsRightShift && ShiftAmount <= -1 && ShiftAmount >= -(int)ElemBits) in tryCombineShiftImm()
7071 DAG.getConstant(-ShiftAmount, MVT::i32)); in tryCombineShiftImm()
7072 else if (!IsRightShift && ShiftAmount >= 0 && ShiftAmount < ElemBits) in tryCombineShiftImm()
7074 DAG.getConstant(ShiftAmount, MVT::i32)); in tryCombineShiftImm()
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| D | AArch64ISelDAGToDAG.cpp | 1781 SDValue &Src, int &ShiftAmount, in isBitfieldPositioningOp() argument
1811 ShiftAmount = countTrailingZeros(NonZeroBits); in isBitfieldPositioningOp()
1812 MaskWidth = CountTrailingOnes_64(NonZeroBits >> ShiftAmount); in isBitfieldPositioningOp()
1817 Src = getLeftShift(CurDAG, Op, ShlImm - ShiftAmount); in isBitfieldPositioningOp()
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| /external/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 200 unsigned &ShiftAmount);
4026 const MCExpr *ShiftAmount; in parsePKHImm() local
4029 if (getParser().parseExpression(ShiftAmount, EndLoc)) { in parsePKHImm()
4033 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); in parsePKHImm()
4107 const MCExpr *ShiftAmount; in parseShifterImm() local
4109 if (getParser().parseExpression(ShiftAmount, EndLoc)) { in parseShifterImm()
4113 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); in parseShifterImm()
4168 const MCExpr *ShiftAmount; in parseRotImm() local
4170 if (getParser().parseExpression(ShiftAmount, EndLoc)) { in parseRotImm()
4174 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); in parseRotImm()
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| /external/llvm/lib/Target/R600/ |
| D | R600ISelLowering.cpp | 1582 SDValue ShiftAmount = in LowerLOAD() local
1589 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, NewLoad, ShiftAmount); in LowerLOAD()
1590 SDValue Sra = DAG.getNode(ISD::SRA, DL, VT, Shl, ShiftAmount); in LowerLOAD()
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