| /external/llvm/utils/TableGen/ |
| D | RegisterInfoEmitter.cpp | 140 ArrayRef<CodeGenSubRegIndex*> SubRegIndices = Bank.getSubRegIndices(); in runEnums() local
141 if (!SubRegIndices.empty()) { in runEnums()
144 SubRegIndices[0]->getNamespace(); in runEnums()
148 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) in runEnums()
149 OS << " " << SubRegIndices[i]->getName() << ",\t// " << i+1 << "\n"; in runEnums()
633 ArrayRef<CodeGenSubRegIndex*> SubRegIndices = RegBank.getSubRegIndices(); in emitComposeSubRegIndices() local
648 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) { in emitComposeSubRegIndices()
651 if (combine(SubRegIndices[i], Rows[r])) { in emitComposeSubRegIndices()
659 Rows.back().resize(SubRegIndices.size()); in emitComposeSubRegIndices()
660 combine(SubRegIndices[i], Rows.back()); in emitComposeSubRegIndices()
[all …]
|
| D | CodeGenRegisters.cpp | 937 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) in CodeGenRegBank()
938 SubRegIndices[i]->updateComponents(*this); in CodeGenRegBank()
1017 SubRegIndices.size() + 1); in createSubRegIndex()
1018 SubRegIndices.push_back(Idx); in createSubRegIndex()
1026 Idx = new CodeGenSubRegIndex(Def, SubRegIndices.size() + 1); in getSubRegIdx()
1027 SubRegIndices.push_back(Idx); in getSubRegIdx()
1179 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) { in computeSubRegIndexLaneMasks()
1180 CodeGenSubRegIndex *Idx = SubRegIndices[i]; in computeSubRegIndexLaneMasks()
1205 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) { in computeSubRegIndexLaneMasks()
1206 unsigned Mask = SubRegIndices[i]->computeLaneMask(); in computeSubRegIndexLaneMasks()
[all …]
|
| D | CodeGenRegisters.h | 450 std::vector<CodeGenSubRegIndex*> SubRegIndices; variable
530 ArrayRef<CodeGenSubRegIndex*> getSubRegIndices() { return SubRegIndices; } in getSubRegIndices()
|
| /external/llvm/lib/MC/ |
| D | MCRegisterInfo.cpp | 31 const uint16_t *SRI = SubRegIndices + get(Reg).SubRegIndices; in getSubReg()
42 const uint16_t *SRI = SubRegIndices + get(Reg).SubRegIndices; in getSubRegIndex()
|
| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZRegisterInfo.td | 62 let SubRegIndices = [subreg_l32, subreg_h32];
69 let SubRegIndices = [subreg_l64, subreg_h64];
154 let SubRegIndices = [subreg_h32];
161 let SubRegIndices = [subreg_l64, subreg_h64];
|
| /external/llvm/include/llvm/MC/ |
| D | MCRegisterInfo.h | 116 uint32_t SubRegIndices; member
165 const uint16_t *SubRegIndices; // Pointer to the subreg lookup variable
260 SubRegIndices = SubIndices; in InitMCRegisterInfo()
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsRegisterInfo.td | 47 let SubRegIndices = [sub_32];
56 let SubRegIndices = [sub_lo, sub_hi];
62 let SubRegIndices = [sub_lo, sub_hi];
69 let SubRegIndices = [sub_64];
75 let SubRegIndices = [sub_lo, sub_hi];
191 let SubRegIndices = [sub_32] in {
238 let SubRegIndices = [sub_dsp16_19, sub_dsp20, sub_dsp21, sub_dsp22,
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCRegisterInfo.td | 39 let SubRegIndices = [sub_32];
64 let SubRegIndices = [sub_64];
72 let SubRegIndices = [sub_64];
81 let SubRegIndices = [sub_128];
180 let SubRegIndices = [sub_lt, sub_gt, sub_eq, sub_un] in {
|
| /external/llvm/lib/Target/X86/ |
| D | X86RegisterInfo.td | 77 let SubRegIndices = [sub_8bit, sub_8bit_hi], CoveredBySubRegs = 1 in {
83 let SubRegIndices = [sub_8bit] in {
92 let SubRegIndices = [sub_8bit], CostPerUse = 1 in {
104 let SubRegIndices = [sub_16bit] in {
128 let SubRegIndices = [sub_32bit] in {
212 let SubRegIndices = [sub_xmm] in {
220 let SubRegIndices = [sub_ymm] in {
|
| /external/llvm/lib/Target/MSP430/ |
| D | MSP430RegisterInfo.td | 48 let SubRegIndices = [subreg_8bit] in {
|
| /external/llvm/lib/Target/R600/ |
| D | R600RegisterInfo.td | 23 let SubRegIndices = [sub0, sub1, sub2, sub3];
32 let SubRegIndices = [sub0, sub1];
|
| D | SIRegisterInfo.td | 26 let SubRegIndices = [sub0, sub1];
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64RegisterInfo.td | 85 let SubRegIndices = [sub_32] in {
245 let SubRegIndices = [bsub] in {
280 let SubRegIndices = [hsub] in {
315 let SubRegIndices = [ssub], RegAltNameIndices = [vreg, vlist1] in {
350 let SubRegIndices = [dsub], RegAltNameIndices = [vreg, vlist1] in {
|
| /external/llvm/lib/Target/Sparc/ |
| D | SparcRegisterInfo.td | 41 let SubRegIndices = [sub_even, sub_odd];
48 let SubRegIndices = [sub_even64, sub_odd64];
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMRegisterInfo.td | 99 let SubRegIndices = [ssub_0, ssub_1] in {
137 let SubRegIndices = [dsub_0, dsub_1] in {
147 let SubRegIndices = [dsub_0, dsub_1] in {
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonRegisterInfo.td | 102 let SubRegIndices = [subreg_loreg, subreg_hireg], CoveredBySubRegs = 1 in {
|
| /external/llvm/include/llvm/Target/ |
| D | Target.td | 96 // SubRegIndices - For each register in SubRegs, specify the SubRegIndex used
99 list<SubRegIndex> SubRegIndices = [];
260 // let SubRegIndices = [sube, subo] in {
278 // SubRegIndices - N SubRegIndex instances. This provides the names of the
280 list<SubRegIndex> SubRegIndices = Indices;
|