| /external/llvm/test/CodeGen/X86/ |
| D | vshift-6.ll | 13 ; VSELECT(r, B, count);
17 ; r = VSELECT(r, C, count);
19 ; VSELECT(r, r+r, count);
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| D | 2011-12-15-vec_shift.ll | 13 ; Make sure we're masking and pcmp'ing the VSELECT conditon vector.
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| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 330 VSELECT, enumerator
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| D | SelectionDAG.h | 703 return getNode(Cond.getValueType().isVector() ? ISD::VSELECT : ISD::SELECT, DL, VT,
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEISelLowering.cpp | 82 setTargetDAGCombine(ISD::VSELECT); in MipsSETargetLowering()
100 setTargetDAGCombine(ISD::VSELECT); in MipsSETargetLowering()
272 setOperationAction(ISD::VSELECT, Ty, Legal); in addMSAIntType()
317 setOperationAction(ISD::VSELECT, Ty, Legal); in addMSAFloatType()
774 return DAG.getNode(ISD::VSELECT, SDLoc(N), Ty, Cond, IfSet, IfClr); in performORCombine()
1087 case ISD::VSELECT: in PerformDAGCombine()
1577 return DAG.getNode(ISD::VSELECT, DL, VecTy, in lowerINTRINSIC_WO_CHAIN()
1590 return DAG.getNode(ISD::VSELECT, DL, VecTy, in lowerINTRINSIC_WO_CHAIN()
1595 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), Op->getOperand(3), in lowerINTRINSIC_WO_CHAIN()
1598 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
[all …]
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorTypes.cpp | 63 case ISD::VSELECT: R = ScalarizeVecRes_VSELECT(N); break; in ScalarizeVectorResult()
419 case ISD::VSELECT: in ScalarizeVectorOperand()
560 case ISD::VSELECT: in SplitVectorResult()
1208 case ISD::VSELECT: in SplitVectorOperand()
1270 DAG.getNode(ISD::VSELECT, DL, LoOpVT, LoMask, LoOp0, LoOp1); in SplitVecOp_VSELECT()
1272 DAG.getNode(ISD::VSELECT, DL, HiOpVT, HiMask, HiOp0, HiOp1); in SplitVecOp_VSELECT()
1561 case ISD::VSELECT: in WidenVectorResult()
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| D | LegalizeVectorOps.cpp | 265 case ISD::VSELECT: in LegalizeOp()
648 case ISD::VSELECT: in Expand()
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| D | SelectionDAGDumper.cpp | 195 case ISD::VSELECT: return "vselect"; in getOperationName()
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| D | LegalizeIntegerTypes.cpp | 70 case ISD::VSELECT: Res = PromoteIntRes_VSELECT(N); break; in PromoteIntegerResult()
526 return DAG.getNode(ISD::VSELECT, SDLoc(N), in PromoteIntRes_VSELECT()
821 case ISD::VSELECT: in PromoteIntegerOperand()
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| D | SelectionDAG.cpp | 6446 case ISD::VSELECT: in UnrollVectorOp()
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| D | SelectionDAGBuilder.cpp | 2911 ISD::VSELECT : ISD::SELECT; in visitSelect()
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| D | DAGCombiner.cpp | 1231 case ISD::VSELECT: return visitVSELECT(N); in visit()
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| /external/llvm/lib/CodeGen/ |
| D | BasicTargetTransformInfo.cpp | 463 ISD = ISD::VSELECT; in getCmpSelInstrCost()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 873 setOperationAction(ISD::VSELECT, VT, Expand); in resetOperationActions()
1084 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom); in resetOperationActions()
1085 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom); in resetOperationActions()
1086 setOperationAction(ISD::VSELECT, MVT::v4i32, Custom); in resetOperationActions()
1087 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom); in resetOperationActions()
1088 setOperationAction(ISD::VSELECT, MVT::v8i16, Custom); in resetOperationActions()
1091 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal); in resetOperationActions()
1207 setOperationAction(ISD::VSELECT, MVT::v4f64, Custom); in resetOperationActions()
1208 setOperationAction(ISD::VSELECT, MVT::v4i64, Custom); in resetOperationActions()
1209 setOperationAction(ISD::VSELECT, MVT::v8i32, Custom); in resetOperationActions()
[all …]
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 468 setOperationAction(ISD::VSELECT, VT, Expand); in PPCTargetLowering()
555 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal); in PPCTargetLowering()
556 setOperationAction(ISD::VSELECT, MVT::v8i16, Legal); in PPCTargetLowering()
557 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal); in PPCTargetLowering()
558 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal); in PPCTargetLowering()
559 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal); in PPCTargetLowering()
8017 RV = DAG.getNode(VT.isVector() ? ISD::VSELECT : ISD::SELECT, dl, VT, in PerformDAGCombine()
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| D | PPCISelDAGToDAG.cpp | 1342 case ISD::VSELECT: in Select()
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| /external/llvm/lib/Target/R600/ |
| D | AMDGPUISelLowering.cpp | 317 setOperationAction(ISD::VSELECT, VT, Expand); in AMDGPUTargetLowering()
353 setOperationAction(ISD::VSELECT, VT, Expand); in AMDGPUTargetLowering()
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| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 400 def vselect : SDNode<"ISD::VSELECT" , SDTVSelect>;
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 363 setTargetDAGCombine(ISD::VSELECT); in AArch64TargetLowering()
524 setOperationAction(ISD::VSELECT, VT.getSimpleVT(), Expand); in addTypeForNEON()
7662 return DAG.getNode(ISD::VSELECT, SDLoc(N), ResVT, SetCC, in performVSelectCombine()
7734 case ISD::VSELECT: in PerformDAGCombine()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 121 setOperationAction(ISD::VSELECT, VT, Expand); in addTypeForNEON()
|