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Searched refs:addReg (Results 1 – 25 of 132) sorted by relevance

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/external/llvm/lib/Target/X86/AsmParser/
DX86AsmInstrumentation.cpp164 EmitInstruction(Out, MCInstBuilder(X86::AND64ri8).addReg(X86::ESP) in EmitCallAsanReport()
165 .addReg(X86::ESP).addImm(-16)); in EmitCallAsanReport()
166 EmitInstruction(Out, MCInstBuilder(X86::PUSH32r).addReg(AddressReg)); in EmitCallAsanReport()
180 EmitInstruction(Out, MCInstBuilder(X86::PUSH32r).addReg(X86::EAX)); in InstrumentMemOperandSmallImpl()
181 EmitInstruction(Out, MCInstBuilder(X86::PUSH32r).addReg(X86::ECX)); in InstrumentMemOperandSmallImpl()
182 EmitInstruction(Out, MCInstBuilder(X86::PUSH32r).addReg(X86::EDX)); in InstrumentMemOperandSmallImpl()
194 Out, MCInstBuilder(X86::MOV32rr).addReg(X86::ECX).addReg(X86::EAX)); in InstrumentMemOperandSmallImpl()
195 EmitInstruction(Out, MCInstBuilder(X86::SHR32ri).addReg(X86::ECX) in InstrumentMemOperandSmallImpl()
196 .addReg(X86::ECX).addImm(3)); in InstrumentMemOperandSmallImpl()
210 MCInstBuilder(X86::TEST8rr).addReg(X86::CL).addReg(X86::CL)); in InstrumentMemOperandSmallImpl()
[all …]
/external/llvm/lib/Target/ARM/
DARMAsmPrinter.cpp982 .addReg(0)); in EmitJump2Table()
1188 .addReg(MI->getOperand(0).getReg()) in EmitInstruction()
1192 .addReg(MI->getOperand(3).getReg())); in EmitInstruction()
1205 .addReg(MI->getOperand(0).getReg()) in EmitInstruction()
1209 .addReg(MI->getOperand(4).getReg())); in EmitInstruction()
1216 .addReg(ARM::LR) in EmitInstruction()
1217 .addReg(ARM::PC) in EmitInstruction()
1220 .addReg(0) in EmitInstruction()
1222 .addReg(0)); in EmitInstruction()
1225 .addReg(MI->getOperand(0).getReg())); in EmitInstruction()
[all …]
DARMFrameLowering.cpp319 .addImm((unsigned)ARMCC::AL).addReg(0) in emitPrologue()
321 .addReg(ARM::R4, RegState::Implicit) in emitPrologue()
331 .addImm((unsigned)ARMCC::AL).addReg(0) in emitPrologue()
332 .addReg(ARM::R12, RegState::Kill) in emitPrologue()
333 .addReg(ARM::R4, RegState::Implicit) in emitPrologue()
340 .addReg(ARM::SP, RegState::Define) in emitPrologue()
341 .addReg(ARM::R4, RegState::Kill) in emitPrologue()
523 .addReg(ARM::SP, RegState::Kill) in emitPrologue()
533 .addReg(ARM::SP, RegState::Kill)); in emitPrologue()
536 .addReg(ARM::R4, RegState::Kill) in emitPrologue()
[all …]
DARMLoadStoreOptimizer.cpp387 .addReg(Base, getKillRegState(true)).addImm(WordOffset * 4) in UpdateBaseRegUses()
388 .addImm(Pred).addReg(PredReg); in UpdateBaseRegUses()
405 .addReg(Base, getKillRegState(true)).addImm(WordOffset * 4) in UpdateBaseRegUses()
406 .addImm(Pred).addReg(PredReg); in UpdateBaseRegUses()
480 .addReg(Base, getKillRegState(BaseKill)) in MergeOps()
481 .addImm(Pred).addReg(PredReg); in MergeOps()
484 .addReg(NewBase, getKillRegState(true)).addImm(Offset) in MergeOps()
485 .addImm(Pred).addReg(PredReg); in MergeOps()
488 .addReg(Base, getKillRegState(BaseKill)).addImm(Offset) in MergeOps()
489 .addImm(Pred).addReg(PredReg).addReg(0); in MergeOps()
[all …]
DARMExpandPseudoInsts.cpp397 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
399 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
401 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
403 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
434 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); in ExpandVLD()
472 MIB.addReg(D0, getUndefRegState(SrcIsUndef)); in ExpandVST()
474 MIB.addReg(D1, getUndefRegState(SrcIsUndef)); in ExpandVST()
476 MIB.addReg(D2, getUndefRegState(SrcIsUndef)); in ExpandVST()
478 MIB.addReg(D3, getUndefRegState(SrcIsUndef)); in ExpandVST()
487 MIB.addReg(SrcReg, RegState::Implicit); // Add implicit uses for src reg. in ExpandVST()
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DThumb2InstrInfo.cpp122 .addReg(SrcReg, getKillRegState(KillSrc))); in copyPhysReg()
145 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
205 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
219 .addReg(BaseReg, RegState::Kill) in emitT2RegPlusImmediate()
220 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags); in emitT2RegPlusImmediate()
237 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags); in emitT2RegPlusImmediate()
242 .addReg(DestReg) in emitT2RegPlusImmediate()
244 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags); in emitT2RegPlusImmediate()
251 .addReg(BaseReg, RegState::Kill) in emitT2RegPlusImmediate()
252 .addReg(DestReg, RegState::Kill) in emitT2RegPlusImmediate()
[all …]
/external/llvm/lib/Target/Hexagon/
DHexagonExpandPredSpillCode.cpp103 .addReg(FP).addReg(HEXAGON_RESERVED_REG_1); in runOnMachineFunction()
105 HEXAGON_RESERVED_REG_2).addReg(SrcReg); in runOnMachineFunction()
108 .addReg(HEXAGON_RESERVED_REG_1) in runOnMachineFunction()
109 .addImm(0).addReg(HEXAGON_RESERVED_REG_2); in runOnMachineFunction()
112 HEXAGON_RESERVED_REG_1).addReg(FP).addImm(Offset); in runOnMachineFunction()
114 HEXAGON_RESERVED_REG_2).addReg(SrcReg); in runOnMachineFunction()
117 .addReg(HEXAGON_RESERVED_REG_1) in runOnMachineFunction()
119 .addReg(HEXAGON_RESERVED_REG_2); in runOnMachineFunction()
123 HEXAGON_RESERVED_REG_2).addReg(SrcReg); in runOnMachineFunction()
126 addReg(FP).addImm(Offset).addReg(HEXAGON_RESERVED_REG_2); in runOnMachineFunction()
[all …]
DHexagonSplitTFRCondSets.cpp116 DestReg).addReg(MI->getOperand(1).getReg()).addReg(SrcReg1); in runOnMachineFunction()
120 DestReg).addReg(MI->getOperand(1).getReg()).addReg(SrcReg2); in runOnMachineFunction()
136 addReg(MI->getOperand(1).getReg()).addReg(SrcReg1); in runOnMachineFunction()
141 addReg(MI->getOperand(1).getReg()). in runOnMachineFunction()
146 addReg(MI->getOperand(1).getReg()). in runOnMachineFunction()
162 addReg(MI->getOperand(1).getReg()). in runOnMachineFunction()
167 addReg(MI->getOperand(1).getReg()). in runOnMachineFunction()
176 addReg(MI->getOperand(1).getReg()).addReg(SrcReg2); in runOnMachineFunction()
192 DestReg).addReg(SrcReg1).addImm(Immed1); in runOnMachineFunction()
195 DestReg).addReg(SrcReg1).addImm(Immed2); in runOnMachineFunction()
[all …]
DHexagonRegisterInfo.cpp180 dstReg).addReg(FrameReg).addReg(dstReg); in eliminateFrameIndex()
184 dstReg).addReg(FrameReg).addImm(Offset); in eliminateFrameIndex()
209 resReg).addReg(FrameReg).addReg(resReg); in eliminateFrameIndex()
213 resReg).addReg(FrameReg).addImm(Offset); in eliminateFrameIndex()
240 TII.get(Hexagon::ADD_rr), ResReg).addReg(FrameReg). in eliminateFrameIndex()
241 addReg(ResReg); in eliminateFrameIndex()
247 TII.get(Hexagon::ADD_ri), ResReg).addReg(FrameReg). in eliminateFrameIndex()
260 dstReg).addReg(FrameReg).addReg(dstReg); in eliminateFrameIndex()
/external/llvm/lib/Target/R600/
DSILowerControlFlow.cpp142 .addReg(AMDGPU::EXEC); in Skip()
161 .addReg(AMDGPU::EXEC); in SkipIfDead()
170 .addReg(AMDGPU::VGPR0) in SkipIfDead()
171 .addReg(AMDGPU::VGPR0) in SkipIfDead()
172 .addReg(AMDGPU::VGPR0) in SkipIfDead()
173 .addReg(AMDGPU::VGPR0); in SkipIfDead()
186 .addReg(Vcc); in If()
189 .addReg(AMDGPU::EXEC) in If()
190 .addReg(Reg); in If()
205 .addReg(Src); // Saved EXEC in Else()
[all …]
/external/llvm/lib/Target/X86/
DX86InstrBuilder.h94 return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0).addReg(0); in addDirectMem()
100 return MIB.addImm(1).addReg(0).addImm(Offset).addReg(0); in addOffset()
110 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset); in addRegOffset()
118 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1) in addRegReg()
119 .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0); in addRegReg()
128 MIB.addReg(AM.Base.Reg); in addFullAddress()
134 MIB.addImm(AM.Scale).addReg(AM.IndexReg); in addFullAddress()
140 return MIB.addReg(0); in addFullAddress()
178 return MIB.addReg(GlobalBaseReg).addImm(1).addReg(0) in addConstantPoolReference()
179 .addConstantPoolIndex(CPI, 0, OpFlags).addReg(0); in addConstantPoolReference()
/external/llvm/lib/Target/SystemZ/
DSystemZAsmPrinter.cpp34 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) in lowerRILow()
38 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) in lowerRILow()
39 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(1).getReg())) in lowerRILow()
48 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg())) in lowerRIHigh()
52 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg())) in lowerRIHigh()
53 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(1).getReg())) in lowerRIHigh()
61 .addReg(MI->getOperand(0).getReg()) in lowerRIEfLow()
62 .addReg(MI->getOperand(1).getReg()) in lowerRIEfLow()
63 .addReg(SystemZMC::getRegAsGR64(MI->getOperand(2).getReg())) in lowerRIEfLow()
74 LoweredMI = MCInstBuilder(SystemZ::BR).addReg(SystemZ::R14D); in EmitInstruction()
[all …]
/external/llvm/lib/Target/XCore/
DXCoreRegisterInfo.cpp71 .addReg(FrameReg) in InsertFPImmInst()
77 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) in InsertFPImmInst()
78 .addReg(FrameReg) in InsertFPImmInst()
84 .addReg(FrameReg) in InsertFPImmInst()
107 .addReg(FrameReg) in InsertFPConstInst()
108 .addReg(ScratchOffset, RegState::Kill) in InsertFPConstInst()
113 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) in InsertFPConstInst()
114 .addReg(FrameReg) in InsertFPConstInst()
115 .addReg(ScratchOffset, RegState::Kill) in InsertFPConstInst()
120 .addReg(FrameReg) in InsertFPConstInst()
[all …]
/external/llvm/lib/Target/Mips/
DMipsLongBranch.cpp234 MIB.addReg(MO.getReg()); in replaceBranch()
294 .addReg(Mips::SP).addImm(-8); in expandToLongBranch()
295 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SW)).addReg(Mips::RA) in expandToLongBranch()
296 .addReg(Mips::SP).addImm(0); in expandToLongBranch()
319 .addReg(Mips::AT) in expandToLongBranch()
326 .addReg(Mips::RA).addReg(Mips::AT); in expandToLongBranch()
328 .addReg(Mips::SP).addImm(0); in expandToLongBranch()
332 .append(BuildMI(*MF, DL, TII->get(Mips::JR)).addReg(Mips::AT)) in expandToLongBranch()
334 .addReg(Mips::SP).addImm(8)); in expandToLongBranch()
338 .addReg(Mips::SP).addImm(8); in expandToLongBranch()
[all …]
DMipsSEInstrInfo.cpp111 .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc)); in copyPhysReg()
132 .addReg(SrcReg, getKillRegState(KillSrc)).addImm(1 << 4) in copyPhysReg()
133 .addReg(DestReg, RegState::ImplicitDefine); in copyPhysReg()
173 MIB.addReg(DestReg, RegState::Define); in copyPhysReg()
176 MIB.addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
179 MIB.addReg(ZeroReg); in copyPhysReg()
221 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill)) in storeRegToStack()
369 BuildMI(MBB, I, DL, get(ADDiu), SP).addReg(SP).addImm(Amount); in adjustStackPtr()
372 BuildMI(MBB, I, DL, get(ADDu), SP).addReg(SP).addReg(Reg, RegState::Kill); in adjustStackPtr()
406 BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(ZEROReg) in loadImmediate()
[all …]
/external/llvm/lib/Target/PowerPC/
DPPCFrameLowering.cpp304 .addReg(SrcReg) in HandleVRSaveUpdate()
308 .addReg(SrcReg, RegState::Kill) in HandleVRSaveUpdate()
313 .addReg(SrcReg) in HandleVRSaveUpdate()
317 .addReg(SrcReg, RegState::Kill) in HandleVRSaveUpdate()
322 .addReg(SrcReg) in HandleVRSaveUpdate()
326 .addReg(SrcReg, RegState::Kill) in HandleVRSaveUpdate()
330 .addReg(DstReg, RegState::Kill) in HandleVRSaveUpdate()
629 MIB.addReg(MustSaveCRs[i], RegState::ImplicitKill); in emitPrologue()
635 .addReg(FPReg) in emitPrologue()
637 .addReg(SPReg); in emitPrologue()
[all …]
DPPCRegisterInfo.cpp309 .addReg(PPC::R31) in lowerDynamicAlloc()
314 .addReg(PPC::X1); in lowerDynamicAlloc()
318 .addReg(PPC::R1); in lowerDynamicAlloc()
339 .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg)) in lowerDynamicAlloc()
340 .addReg(NegSizeReg1, RegState::Kill); in lowerDynamicAlloc()
345 .addReg(Reg, RegState::Kill) in lowerDynamicAlloc()
346 .addReg(PPC::X1) in lowerDynamicAlloc()
347 .addReg(NegSizeReg, getKillRegState(KillNegSizeReg)); in lowerDynamicAlloc()
349 .addReg(PPC::X1) in lowerDynamicAlloc()
364 .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg)) in lowerDynamicAlloc()
[all …]
DPPCAsmPrinter.cpp488 .addReg(MI->getOperand(0).getReg()) in EmitInstruction()
489 .addReg(PPC::X2) in EmitInstruction()
520 .addReg(MI->getOperand(0).getReg()) in EmitInstruction()
523 .addReg(MI->getOperand(0).getReg()) in EmitInstruction()
524 .addReg(MI->getOperand(0).getReg()) in EmitInstruction()
539 .addReg(MI->getOperand(0).getReg()) in EmitInstruction()
540 .addReg(PPC::X2) in EmitInstruction()
555 .addReg(MI->getOperand(0).getReg()) in EmitInstruction()
556 .addReg(MI->getOperand(1).getReg()) in EmitInstruction()
591 .addReg(MI->getOperand(0).getReg()) in EmitInstruction()
[all …]
/external/mesa3d/src/gallium/drivers/radeon/
DR600InstrInfo.cpp59 .addReg(RI.getSubReg(DestReg, SubRegIndex), RegState::Define) in copyPhysReg()
60 .addReg(RI.getSubReg(SrcReg, SubRegIndex)) in copyPhysReg()
62 .addReg(0) // PREDICATE_BIT in copyPhysReg()
63 .addReg(DestReg, RegState::Define | RegState::Implicit); in copyPhysReg()
72 .addReg(SrcReg, getKillRegState(KillSrc)) in copyPhysReg()
74 .addReg(0); // PREDICATE_BIT in copyPhysReg()
82 MachineInstrBuilder(MI).addReg(DstReg, RegState::Define); in getMovImmInstr()
83 MachineInstrBuilder(MI).addReg(AMDGPU::ALU_LITERAL_X); in getMovImmInstr()
85 MachineInstrBuilder(MI).addReg(0); // PREDICATE_BIT in getMovImmInstr()
271 BuildMI(&MBB, DL, get(AMDGPU::JUMP)).addMBB(TBB).addReg(0); in InsertBranch()
[all …]
DR600ISelLowering.cpp69 .addReg(AMDGPU::PRED_SEL_OFF); in EmitInstrWithCustomInserter()
80 .addReg(AMDGPU::PRED_SEL_OFF); in EmitInstrWithCustomInserter()
92 .addReg(AMDGPU::PRED_SEL_OFF); in EmitInstrWithCustomInserter()
103 .addReg(ConstantReg); in EmitInstrWithCustomInserter()
131 .addReg(AMDGPU::ALU_LITERAL_X) in EmitInstrWithCustomInserter()
132 .addReg(AMDGPU::PRED_SEL_OFF) in EmitInstrWithCustomInserter()
136 .addReg(ShiftValue) in EmitInstrWithCustomInserter()
137 .addReg(AMDGPU::PRED_SEL_OFF); in EmitInstrWithCustomInserter()
140 .addReg(NewAddr) in EmitInstrWithCustomInserter()
173 .addReg(t0, RegState::Implicit) in EmitInstrWithCustomInserter()
[all …]
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
DR600InstrInfo.cpp59 .addReg(RI.getSubReg(DestReg, SubRegIndex), RegState::Define) in copyPhysReg()
60 .addReg(RI.getSubReg(SrcReg, SubRegIndex)) in copyPhysReg()
62 .addReg(0) // PREDICATE_BIT in copyPhysReg()
63 .addReg(DestReg, RegState::Define | RegState::Implicit); in copyPhysReg()
72 .addReg(SrcReg, getKillRegState(KillSrc)) in copyPhysReg()
74 .addReg(0); // PREDICATE_BIT in copyPhysReg()
82 MachineInstrBuilder(MI).addReg(DstReg, RegState::Define); in getMovImmInstr()
83 MachineInstrBuilder(MI).addReg(AMDGPU::ALU_LITERAL_X); in getMovImmInstr()
85 MachineInstrBuilder(MI).addReg(0); // PREDICATE_BIT in getMovImmInstr()
271 BuildMI(&MBB, DL, get(AMDGPU::JUMP)).addMBB(TBB).addReg(0); in InsertBranch()
[all …]
DR600ISelLowering.cpp69 .addReg(AMDGPU::PRED_SEL_OFF); in EmitInstrWithCustomInserter()
80 .addReg(AMDGPU::PRED_SEL_OFF); in EmitInstrWithCustomInserter()
92 .addReg(AMDGPU::PRED_SEL_OFF); in EmitInstrWithCustomInserter()
103 .addReg(ConstantReg); in EmitInstrWithCustomInserter()
131 .addReg(AMDGPU::ALU_LITERAL_X) in EmitInstrWithCustomInserter()
132 .addReg(AMDGPU::PRED_SEL_OFF) in EmitInstrWithCustomInserter()
136 .addReg(ShiftValue) in EmitInstrWithCustomInserter()
137 .addReg(AMDGPU::PRED_SEL_OFF); in EmitInstrWithCustomInserter()
140 .addReg(NewAddr) in EmitInstrWithCustomInserter()
173 .addReg(t0, RegState::Implicit) in EmitInstrWithCustomInserter()
[all …]
/external/llvm/lib/Target/AArch64/
DAArch64ExpandPseudoInsts.cpp100 .addReg(AArch64::XZR) in tryOrrMovk()
109 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in tryOrrMovk()
110 .addReg(DstReg) in tryOrrMovk()
167 .addReg(AArch64::XZR) in tryToreplicateChunks()
186 .addReg(DstReg, in tryToreplicateChunks()
188 .addReg(DstReg) in tryToreplicateChunks()
211 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in tryToreplicateChunks()
212 .addReg(DstReg) in tryToreplicateChunks()
350 .addReg(AArch64::XZR) in trySequenceOfOnes()
360 .addReg(DstReg, in trySequenceOfOnes()
[all …]
DAArch64InstrInfo.cpp264 BuildMI(&MBB, DL, get(Cond[1].getImm())).addReg(Cond[2].getReg()); in instantiateCondBranch()
453 .addReg(SrcReg) in insertSelect()
459 .addReg(SrcReg) in insertSelect()
482 .addReg(Cond[2].getReg()) in insertSelect()
487 .addReg(Cond[2].getReg()) in insertSelect()
540 BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(TrueReg).addReg(FalseReg).addImm( in insertSelect()
1260 return MIB.addReg(Reg, State); in AddSubReg()
1263 return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State); in AddSubReg()
1264 return MIB.addReg(Reg, State, SubIdx); in AddSubReg()
1321 .addReg(SrcRegX, RegState::Undef) in copyPhysReg()
[all …]
/external/llvm/lib/Target/MSP430/
DMSP430FrameLowering.cpp67 .addReg(MSP430::FPW, RegState::Kill); in emitPrologue()
71 .addReg(MSP430::SPW); in emitPrologue()
99 .addReg(MSP430::SPW).addImm(NumBytes); in emitPrologue()
157 TII.get(MSP430::MOV16rr), MSP430::SPW).addReg(MSP430::FPW); in emitEpilogue()
162 .addReg(MSP430::SPW).addImm(CSSize); in emitEpilogue()
171 .addReg(MSP430::SPW).addImm(NumBytes); in emitEpilogue()
200 .addReg(Reg, RegState::Kill); in spillCalleeSavedRegisters()
249 .addReg(MSP430::SPW).addImm(Amount); in eliminateCallFramePseudoInstr()
258 .addReg(MSP430::SPW).addImm(Amount); in eliminateCallFramePseudoInstr()
276 MSP430::SPW).addReg(MSP430::SPW).addImm(CalleeAmt); in eliminateCallFramePseudoInstr()

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