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Searched refs:getNode (Results 1 – 25 of 261) sorted by relevance

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/external/llvm/lib/CodeGen/SelectionDAG/
DDAGCombiner.cpp536 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(), in GetNegatedExpression()
541 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(), in GetNegatedExpression()
555 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(), in GetNegatedExpression()
566 return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(), in GetNegatedExpression()
572 return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(), in GetNegatedExpression()
579 return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(), in GetNegatedExpression()
583 return DAG.getNode(ISD::FP_ROUND, SDLoc(Op), Op.getValueType(), in GetNegatedExpression()
605 !TLI.isConstTrueVal(N.getOperand(2).getNode()) || in isSetCCEquivalent()
606 !TLI.isConstFalseVal(N.getOperand(3).getNode())) in isSetCCEquivalent()
620 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse()) in isOneUseSetCC()
[all …]
DLegalizeVectorOps.cpp179 for (unsigned i = 0, e = Op.getNode()->getNumValues(); i != e; ++i) in TranslateLegalizeResults()
190 SDNode* Node = Op.getNode(); in LegalizeOp()
197 SDValue Result = SDValue(DAG.UpdateNodeOperands(Op.getNode(), Ops), 0); in LegalizeOp()
200 LoadSDNode *LD = cast<LoadSDNode>(Op.getNode()); in LegalizeOp()
209 StoreSDNode *ST = cast<StoreSDNode>(Op.getNode()); in LegalizeOp()
320 if (Tmp1.getNode()) { in LegalizeOp()
360 assert(Op.getNode()->getNumValues() == 1 && in Promote()
368 Operands[j] = DAG.getNode(ISD::BITCAST, dl, NVT, Op.getOperand(j)); in Promote()
373 Op = DAG.getNode(Op.getOpcode(), dl, NVT, Operands); in Promote()
375 return DAG.getNode(ISD::BITCAST, dl, VT, Op); in Promote()
[all …]
DLegalizeDAG.cpp175 ReplacedNode(Old.getNode()); in ReplaceNode()
325 SDValue Result = DAG.getNode(ISD::BITCAST, dl, intVT, Val); in ExpandUnalignedStore()
366 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, in ExpandUnalignedStore()
368 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); in ExpandUnalignedStore()
390 SDValue Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores); in ExpandUnalignedStore()
406 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount); in ExpandUnalignedStore()
414 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, in ExpandUnalignedStore()
423 DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2); in ExpandUnalignedStore()
446 SDValue Result = DAG.getNode(ISD::BITCAST, dl, LoadedVT, newLoad); in ExpandUnalignedLoad()
448 Result = DAG.getNode(VT.isFloatingPoint() ? ISD::FP_EXTEND : in ExpandUnalignedLoad()
[all …]
DSelectionDAGBuilder.cpp137 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]); in getCopyFromParts()
138 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]); in getCopyFromParts()
144 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi); in getCopyFromParts()
158 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi); in getCopyFromParts()
159 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi, in getCopyFromParts()
162 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo); in getCopyFromParts()
163 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi); in getCopyFromParts()
170 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]); in getCopyFromParts()
171 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]); in getCopyFromParts()
174 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi); in getCopyFromParts()
[all …]
DLegalizeIntegerTypes.cpp147 if (Res.getNode()) in PromoteIntegerResult()
160 return DAG.getNode(ISD::AssertSext, SDLoc(N), in PromoteIntRes_AssertSext()
167 return DAG.getNode(ISD::AssertZext, SDLoc(N), in PromoteIntRes_AssertZext()
249 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetPromotedInteger(InOp)); in PromoteIntRes_BITCAST()
253 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp)); in PromoteIntRes_BITCAST()
260 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, in PromoteIntRes_BITCAST()
274 InOp = DAG.getNode(ISD::ANY_EXTEND, dl, in PromoteIntRes_BITCAST()
278 return DAG.getNode(ISD::BITCAST, dl, NOutVT, InOp); in PromoteIntRes_BITCAST()
285 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetWidenedVector(InOp)); in PromoteIntRes_BITCAST()
288 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, in PromoteIntRes_BITCAST()
[all …]
DLegalizeTypesGeneric.cpp56 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
57 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
66 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
67 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
73 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
74 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
79 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
80 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
90 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
91 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
[all …]
DTargetLowering.cpp206 SDValue Tmp = DAG.getNode(ISD::SETCC, dl, in softenSetCCOperands()
211 NewLHS = DAG.getNode(ISD::SETCC, dl, in softenSetCCOperands()
214 NewLHS = DAG.getNode(ISD::OR, dl, Tmp.getValueType(), Tmp, NewLHS); in softenSetCCOperands()
302 SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0), in ShrinkDemandedConstant()
327 assert(Op.getNode()->getNumValues() == 1 && in ShrinkDemandedOp()
336 if (!Op.getNode()->hasOneUse()) in ShrinkDemandedOp()
351 SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT, in ShrinkDemandedOp()
352 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, in ShrinkDemandedOp()
353 Op.getNode()->getOperand(0)), in ShrinkDemandedOp()
354 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, in ShrinkDemandedOp()
[all …]
DLegalizeVectorTypes.cpp131 if (R.getNode()) in ScalarizeVectorResult()
138 return DAG.getNode(N->getOpcode(), SDLoc(N), in ScalarizeVecRes_BinOp()
146 return DAG.getNode(N->getOpcode(), SDLoc(N), in ScalarizeVecRes_TernaryOp()
158 return DAG.getNode(ISD::BITCAST, SDLoc(N), in ScalarizeVecRes_BITCAST()
168 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, InOp); in ScalarizeVecRes_BUILD_VECTOR()
184 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N), in ScalarizeVecRes_EXTRACT_SUBVECTOR()
192 return DAG.getNode(ISD::FP_ROUND, SDLoc(N), in ScalarizeVecRes_FP_ROUND()
198 return DAG.getNode(ISD::FPOWI, SDLoc(N), in ScalarizeVecRes_FPOWI()
209 Op = DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, Op); in ScalarizeVecRes_INSERT_VECTOR_ELT()
238 return DAG.getNode(N->getOpcode(), SDLoc(N), DestVT, Op); in ScalarizeVecRes_UnaryOp()
[all …]
DResourcePriorityQueue.cpp80 const SDNode *ScegN = PredSU->getNode(); in numberRCValPredInSU()
118 const SDNode *ScegN = SuccSU->getNode(); in numberRCValSuccInSU()
136 MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo()); in numberRCValSuccInSU()
249 if (!SU || !SU->getNode()) in isResourceAvailable()
254 if (SU->getNode()->getGluedNode()) in isResourceAvailable()
259 if (SU->getNode()->isMachineOpcode()) in isResourceAvailable()
260 switch (SU->getNode()->getMachineOpcode()) { in isResourceAvailable()
263 SU->getNode()->getMachineOpcode()))) in isResourceAvailable()
294 if (!isResourceAvailable(SU) || SU->getNode()->getGluedNode()) { in reserveResources()
299 if (SU->getNode() && SU->getNode()->isMachineOpcode()) { in reserveResources()
[all …]
DLegalizeTypes.cpp104 assert(NewVal.getNode()->getNodeId() != NewNode && in PerformExpensiveChecks()
273 if (IgnoreNodeResults(N->getOperand(i).getNode())) in run()
418 if (!IgnoreNodeResults(I->getOperand(i).getNode()) && in run()
478 if (Op.getNode()->getNodeId() == Processed) in AnalyzeNewNode()
524 Val.setNode(AnalyzeNewNode(Val.getNode())); in AnalyzeNewValue()
525 if (Val.getNode()->getNodeId() == Processed) in AnalyzeNewValue()
560 assert(I->first.getNode() != N); in ExpungeNode()
566 assert(I->first.getNode() != N); in ExpungeNode()
572 assert(I->first.getNode() != N); in ExpungeNode()
578 assert(I->first.getNode() != N); in ExpungeNode()
[all …]
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
DAMDGPUISelLowering.cpp72 return DAG.getNode(AMDGPUISD::RET_FLAG, DL, MVT::Other, Chain); in LowerReturn()
84 Op.getNode()->dump(); in LowerOperation()
113 return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1)); in LowerINTRINSIC_WO_CHAIN()
115 return DAG.getNode(ISD::FABS, DL, VT, Op.getOperand(1)); in LowerINTRINSIC_WO_CHAIN()
119 return DAG.getNode(AMDGPUISD::FRACT, DL, VT, Op.getOperand(1)); in LowerINTRINSIC_WO_CHAIN()
121 return DAG.getNode(AMDGPUISD::MAD, DL, VT, Op.getOperand(1), in LowerINTRINSIC_WO_CHAIN()
124 return DAG.getNode(AMDGPUISD::FMAX, DL, VT, Op.getOperand(1), in LowerINTRINSIC_WO_CHAIN()
127 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Op.getOperand(1), in LowerINTRINSIC_WO_CHAIN()
130 return DAG.getNode(AMDGPUISD::UMAX, DL, VT, Op.getOperand(1), in LowerINTRINSIC_WO_CHAIN()
133 return DAG.getNode(AMDGPUISD::FMIN, DL, VT, Op.getOperand(1), in LowerINTRINSIC_WO_CHAIN()
[all …]
DAMDILISelLowering.cpp329 DST = SDValue(Op.getNode(), 0); in LowerSDIV()
348 DST = SDValue(Op.getNode(), 0); in LowerSREM()
362 Nodes1 = DAG.getNode(AMDGPUISD::VBUILD, in LowerBUILD_VECTOR()
384 Nodes1 = DAG.getNode( in LowerBUILD_VECTOR()
395 Nodes1 = DAG.getNode( in LowerBUILD_VECTOR()
406 Nodes1 = DAG.getNode( in LowerBUILD_VECTOR()
434 Data = DAG.getNode(ISD::ZERO_EXTEND, DL, IVT, Data); in LowerSIGN_EXTEND_INREG()
440 Data = DAG.getNode(ISD::SHL, DL, DVT, Data, Shift); in LowerSIGN_EXTEND_INREG()
442 Data = DAG.getNode(ISD::SRA, DL, DVT, Data, Shift); in LowerSIGN_EXTEND_INREG()
480 Result = DAG.getNode( in LowerBRCOND()
[all …]
/external/mesa3d/src/gallium/drivers/radeon/
DAMDGPUISelLowering.cpp72 return DAG.getNode(AMDGPUISD::RET_FLAG, DL, MVT::Other, Chain); in LowerReturn()
84 Op.getNode()->dump(); in LowerOperation()
113 return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1)); in LowerINTRINSIC_WO_CHAIN()
115 return DAG.getNode(ISD::FABS, DL, VT, Op.getOperand(1)); in LowerINTRINSIC_WO_CHAIN()
119 return DAG.getNode(AMDGPUISD::FRACT, DL, VT, Op.getOperand(1)); in LowerINTRINSIC_WO_CHAIN()
121 return DAG.getNode(AMDGPUISD::MAD, DL, VT, Op.getOperand(1), in LowerINTRINSIC_WO_CHAIN()
124 return DAG.getNode(AMDGPUISD::FMAX, DL, VT, Op.getOperand(1), in LowerINTRINSIC_WO_CHAIN()
127 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Op.getOperand(1), in LowerINTRINSIC_WO_CHAIN()
130 return DAG.getNode(AMDGPUISD::UMAX, DL, VT, Op.getOperand(1), in LowerINTRINSIC_WO_CHAIN()
133 return DAG.getNode(AMDGPUISD::FMIN, DL, VT, Op.getOperand(1), in LowerINTRINSIC_WO_CHAIN()
[all …]
DAMDILISelLowering.cpp329 DST = SDValue(Op.getNode(), 0); in LowerSDIV()
348 DST = SDValue(Op.getNode(), 0); in LowerSREM()
362 Nodes1 = DAG.getNode(AMDGPUISD::VBUILD, in LowerBUILD_VECTOR()
384 Nodes1 = DAG.getNode( in LowerBUILD_VECTOR()
395 Nodes1 = DAG.getNode( in LowerBUILD_VECTOR()
406 Nodes1 = DAG.getNode( in LowerBUILD_VECTOR()
434 Data = DAG.getNode(ISD::ZERO_EXTEND, DL, IVT, Data); in LowerSIGN_EXTEND_INREG()
440 Data = DAG.getNode(ISD::SHL, DL, DVT, Data, Shift); in LowerSIGN_EXTEND_INREG()
442 Data = DAG.getNode(ISD::SRA, DL, DVT, Data, Shift); in LowerSIGN_EXTEND_INREG()
480 Result = DAG.getNode( in LowerBRCOND()
[all …]
/external/llvm/lib/Target/R600/
DAMDGPUISelLowering.cpp495 return DAG.getNode(AMDGPUISD::RET_FLAG, DL, MVT::Other, Chain); in LowerReturn()
525 Op.getNode()->dump(); in LowerOperation()
561 SDNode *Node = LowerLOAD(SDValue(N, 0), DAG).getNode(); in ReplaceNodeResults()
574 if (Lowered.getNode()) in ReplaceNodeResults()
626 SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, InitPtr, Offset); in LowerConstantInitializer()
632 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains); in LowerConstantInitializer()
650 SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, InitPtr, Offset); in LowerConstantInitializer()
656 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains); in LowerConstantInitializer()
751 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(), Args); in LowerCONCAT_VECTORS()
763 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(), Args); in LowerEXTRACT_SUBVECTOR()
[all …]
DR600ISelLowering.cpp583 assert((!Result.getNode() || in LowerOperation()
584 Result.getNode()->getNumValues() == 2) && in LowerOperation()
613 return DAG.getNode(AMDGPUISD::EXPORT, SDLoc(Op), Op.getValueType(), Args); in LowerOperation()
689 return DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v2f32, in LowerOperation()
763 return DAG.getNode(AMDGPUISD::TEXTURE_FETCH, DL, MVT::v4f32, TexArgs); in LowerOperation()
767 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), in LowerOperation()
769 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2), in LowerOperation()
771 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), in LowerOperation()
773 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2), in LowerOperation()
775 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), in LowerOperation()
[all …]
/external/llvm/lib/Target/AArch64/
DAArch64ISelLowering.cpp982 return DAG.getNode(AArch64ISD::FCMP, dl, VT, LHS, RHS); in emitComparison()
1016 return DAG.getNode(Opcode, dl, DAG.getVTList(VT, MVT::i32), LHS, RHS) in emitComparison()
1022 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) { in getAArch64Cmp()
1122 LHS = DAG.getNode(ExtendOpc, DL, MVT::i64, LHS); in getAArch64XALUOOp()
1123 RHS = DAG.getNode(ExtendOpc, DL, MVT::i64, RHS); in getAArch64XALUOOp()
1124 SDValue Mul = DAG.getNode(ISD::MUL, DL, MVT::i64, LHS, RHS); in getAArch64XALUOOp()
1125 SDValue Add = DAG.getNode(ISD::ADD, DL, MVT::i64, Mul, in getAArch64XALUOOp()
1131 Value = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Add); in getAArch64XALUOOp()
1138 SDValue UpperBits = DAG.getNode(ISD::SRL, DL, MVT::i64, Add, in getAArch64XALUOOp()
1140 UpperBits = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, UpperBits); in getAArch64XALUOOp()
[all …]
/external/llvm/lib/Target/ARM/
DARMISelLowering.cpp1292 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi); in LowerCallResult()
1295 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64); in LowerCallResult()
1296 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val, in LowerCallResult()
1309 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi); in LowerCallResult()
1310 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val, in LowerCallResult()
1324 Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val); in LowerCallResult()
1343 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); in LowerMemOpCallTo()
1357 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl, in PassF64ArgInRegs()
1366 if (!StackPtr.getNode()) in PassF64ArgInRegs()
1459 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
[all …]
/external/llvm/lib/Target/Mips/
DMipsSEISelLowering.cpp391 SDNode *ADDCNode = ADDENode->getOperand(2).getNode(); in selectMADD()
398 SDNode *MultNode = MultHi.getNode(); in selectMADD()
402 if (MultLo.getNode() != MultNode) in selectMADD()
427 SDValue ACCIn = CurDAG->getNode(MipsISD::MTLOHI, DL, MVT::Untyped, in selectMADD()
434 SDValue MAdd = CurDAG->getNode(MultOpc, DL, MVT::Untyped, in selectMADD()
441 SDValue LoOut = CurDAG->getNode(MipsISD::MFLO, DL, MVT::i32, MAdd); in selectMADD()
445 SDValue HiOut = CurDAG->getNode(MipsISD::MFHI, DL, MVT::i32, MAdd); in selectMADD()
463 SDNode *SUBCNode = SUBENode->getOperand(2).getNode(); in selectMSUB()
470 SDNode *MultNode = MultHi.getNode(); in selectMSUB()
474 if (MultLo.getNode() != MultNode) in selectMSUB()
[all …]
/external/llvm/lib/Target/XCore/
DXCoreISelLowering.cpp222 case ISD::SUB: return ExpandADDSUB(Op.getNode(), DAG); in LowerOperation()
263 return DAG.getNode(XCoreISD::PCRelativeWrapper, dl, MVT::i32, GA); in getGlobalAddressWrapper()
268 return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, MVT::i32, GA); in getGlobalAddressWrapper()
270 return DAG.getNode(XCoreISD::DPRelativeWrapper, dl, MVT::i32, GA); in getGlobalAddressWrapper()
300 GA = DAG.getNode(ISD::ADD, DL, MVT::i32, GA, Remaining); in LowerGlobalAddress()
324 return DAG.getNode(XCoreISD::PCRelativeWrapper, DL, getPointerTy(), Result); in LowerBlockAddress()
342 return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, MVT::i32, Res); in LowerConstantPool()
364 return DAG.getNode(XCoreISD::BR_JT, dl, MVT::Other, Chain, TargetJT, Index); in LowerBR_JT()
367 SDValue ScaledIndex = DAG.getNode(ISD::SHL, dl, MVT::i32, Index, in LowerBR_JT()
369 return DAG.getNode(XCoreISD::BR_JT32, dl, MVT::Other, Chain, TargetJT, in LowerBR_JT()
[all …]
/external/llvm/lib/Target/X86/
DX86ISelLowering.cpp101 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT, in ExtractSubVector()
106 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, in ExtractSubVector()
153 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, in InsertSubVector()
1770 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy()); in getPICJumpTableRelocBase()
1894 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy); in LowerReturn()
1896 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy); in LowerReturn()
1898 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy); in LowerReturn()
1900 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy); in LowerReturn()
1926 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy); in LowerReturn()
1937 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy); in LowerReturn()
[all …]
DX86ISelDAGToDAG.cpp85 IndexReg.getNode() != nullptr || Base_Reg.getNode() != nullptr; in hasBaseOrIndexReg()
93 dyn_cast_or_null<RegisterSDNode>(Base_Reg.getNode())) in isRIPRelative()
107 if (Base_Reg.getNode()) in dump()
108 Base_Reg.getNode()->dump(); in dump()
114 if (IndexReg.getNode()) in dump()
115 IndexReg.getNode()->dump(); in dump()
267 if (AM.Segment.getNode()) in getAddressOperands()
375 if (Chain.getNode() == Load.getNode()) in MoveBelowOrigChain()
381 if (Chain.getOperand(i).getNode() == Load.getNode()) in MoveBelowOrigChain()
386 CurDAG->getNode(ISD::TokenFactor, SDLoc(Load), MVT::Other, Ops); in MoveBelowOrigChain()
[all …]
/external/llvm/lib/Target/SystemZ/
DSystemZSelectionDAGInfo.cpp48 return DAG.getNode(Loop, DL, MVT::Other, Chain, Dst, Src, in emitMemMem()
51 return DAG.getNode(Sequence, DL, MVT::Other, Chain, Dst, Src, in emitMemMem()
114 Dst = DAG.getNode(ISD::ADD, DL, PtrVT, Dst, in EmitTargetCodeForMemset()
119 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chain1, Chain2); in EmitTargetCodeForMemset()
128 SDValue Dst2 = DAG.getNode(ISD::ADD, DL, PtrVT, Dst, in EmitTargetCodeForMemset()
133 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chain1, Chain2); in EmitTargetCodeForMemset()
148 SDValue DstPlus1 = DAG.getNode(ISD::ADD, DL, PtrVT, Dst, in EmitTargetCodeForMemset()
171 return DAG.getNode(SystemZISD::CLC_LOOP, DL, VTs, Chain, Src1, Src2, in emitCLC()
174 return DAG.getNode(SystemZISD::CLC, DL, VTs, Chain, Src1, Src2, in emitCLC()
183 SDValue IPM = DAG.getNode(SystemZISD::IPM, DL, MVT::i32, Glue); in addIPMSequence()
[all …]
/external/llvm/lib/Target/PowerPC/
DPPCISelLowering.cpp839 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) { in isFloatingPointZero()
1088 if (!UniquedVals[i&(Multiple-1)].getNode()) in get_VSPLTI_elt()
1103 if (!UniquedVals[i].getNode()) continue; // Must have been undefs. in get_VSPLTI_elt()
1110 if (!UniquedVals[Multiple-1].getNode()) in get_VSPLTI_elt()
1117 if (!UniquedVals[Multiple-1].getNode()) in get_VSPLTI_elt()
1130 if (!OpVal.getNode()) in get_VSPLTI_elt()
1136 if (!OpVal.getNode()) return SDValue(); // All UNDEF: use implicit def. in get_VSPLTI_elt()
1195 return isIntS16Immediate(Op.getNode(), Imm); in isIntS16Immediate()
1445 if (Val == Base || Base.getNode()->isPredecessorOf(Val.getNode())) in getPreIndexedAddressParts()
1524 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero); in LowerLabelRef()
[all …]
/external/llvm/lib/Target/NVPTX/
DNVPTXISelLowering.cpp489 return DAG.getNode(NVPTXISD::Wrapper, dl, getPointerTy(), Op); in LowerGlobalAddress()
710 Chain = DAG.getNode(NVPTXISD::DeclareParam, dl, DeclareParamVTs, in LowerCall()
720 StVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i16, StVal); in LowerCall()
748 Chain = DAG.getNode(NVPTXISD::DeclareParam, dl, DeclareParamVTs, in LowerCall()
764 Elt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Elt); in LowerCall()
779 Elt0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Elt0); in LowerCall()
780 Elt1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Elt1); in LowerCall()
824 StoreVal = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal); in LowerCall()
831 DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal); in LowerCall()
843 DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal); in LowerCall()
[all …]

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