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Searched refs:getNumDefs (Results 1 – 25 of 27) sorted by relevance

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/external/llvm/lib/CodeGen/SelectionDAG/
DFastISel.cpp1358 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in FastEmitInst_r()
1360 if (II.getNumDefs() >= 1) in FastEmitInst_r()
1380 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in FastEmitInst_rr()
1381 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1); in FastEmitInst_rr()
1383 if (II.getNumDefs() >= 1) in FastEmitInst_rr()
1405 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in FastEmitInst_rrr()
1406 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1); in FastEmitInst_rrr()
1407 Op2 = constrainOperandRegClass(II, Op2, II.getNumDefs() + 2); in FastEmitInst_rrr()
1409 if (II.getNumDefs() >= 1) in FastEmitInst_rrr()
1432 RC = TII.getRegClass(II, II.getNumDefs(), &TRI, *FuncInfo.MF); in FastEmitInst_ri()
[all …]
DScheduleDAGSDNodes.cpp125 if (ResNo >= II.getNumDefs() && in CheckForPhysRegDependency()
126 II.ImplicitDefs[ResNo - II.getNumDefs()] == Reg) { in CheckForPhysRegDependency()
459 if (NumUsed > TII->get(N->getMachineOpcode()).getNumDefs()) in AddSchedEdges()
550 unsigned NRegDefs = SchedDAG->TII->get(Node->getMachineOpcode()).getNumDefs(); in InitNodeNumDefs()
637 OpIdx += TII->get(Use->getMachineOpcode()).getNumDefs(); in computeOperandLatency()
DInstrEmitter.cpp134 if (i+II.getNumDefs() < II.getNumOperands()) { in EmitCopyFromReg()
136 TII->getRegClass(II, i+II.getNumDefs(), TRI, *MF)); in EmitCopyFromReg()
215 for (unsigned i = 0; i < II.getNumDefs(); ++i) { in CreateVirtualRegisters()
738 unsigned NumDefs = II.getNumDefs(); in EmitMachineNode()
DScheduleDAGRRList.cpp1196 unsigned NumRes = MCID.getNumDefs(); in getPhysicalRegisterVT()
1971 unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs(); in MayReduceRegPressure()
2018 unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs(); in RegPressureDiff()
2148 unsigned NumDefs = TII->get(PN->getMachineOpcode()).getNumDefs(); in unscheduledNode()
2165 unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs(); in unscheduledNode()
2686 unsigned NumRes = MCID.getNumDefs(); in canClobber()
2744 unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs(); in canClobberPhysRegDefs()
2913 unsigned NumRes = MCID.getNumDefs(); in AddPseudoTwoAddrDeps()
DResourcePriorityQueue.cpp559 NodeNumDefs = std::min(N->getNumValues(), TID.getNumDefs()); in initNumRegDefsLeft()
DScheduleDAGFast.cpp438 unsigned NumRes = MCID.getNumDefs(); in getPhysicalRegisterVT()
/external/llvm/lib/CodeGen/
DPeepholeOptimizer.cpp500 if (Copy.getDesc().getNumDefs() != 1) in getCopyOrBitcastDefUseIdx()
607 if (MCID.getNumDefs() != 1) in isLoadFoldable()
629 if (MCID.getNumDefs() != 1) in isMoveImmediate()
742 for (unsigned i = MIDesc.getNumDefs(); i != MIDesc.getNumOperands(); in runOnMachineFunction()
810 if (Def->getDesc().getNumDefs() != 1) in getNextSourceFromBitcast()
976 (DefIdx < Def->getDesc().getNumDefs() || Def->getDesc().isVariadic()) && in getNextSourceImpl()
DExecutionDepsFix.cpp507 e = MI->isVariadic() ? MI->getNumOperands() : MCID.getNumDefs(); in processDefs()
580 for (unsigned i = mi->getDesc().getNumDefs(), in visitHardInstr()
590 for (unsigned i = 0, e = mi->getDesc().getNumDefs(); i != e; ++i) { in visitHardInstr()
609 for (unsigned i = mi->getDesc().getNumDefs(), in visitSoftInstr()
DTargetInstrInfo.cpp124 bool HasDef = MCID.getNumDefs(); in commuteInstruction()
191 SrcOpIdx1 = MCID.getNumDefs(); in findCommutedOpIndices()
DMachineLICM.cpp1048 unsigned NumDefs = MI.getDesc().getNumDefs(); in IsCheapInstruction()
1261 if (MID.getNumDefs() != 1) return nullptr; in ExtractHoistableLoad()
DMachineCSE.cpp522 unsigned NumDefs = MI->getDesc().getNumDefs() + in ProcessBlock()
DMachineVerifier.cpp821 if (MONum < MCID.getNumDefs()) { in visitMachineOperand()
875 if (MONum < MCID.getNumDefs()) { in visitMachineOperand()
DRegAllocFast.cpp951 (hasTiedOps && (hasPhysDefs || MCID.getNumDefs() > 1))) { in AllocateBasicBlock()
DTwoAddressInstructionPass.cpp1190 if (UnfoldMCID.getNumDefs() == 1) { in tryInstructionTransform()
DRegisterCoalescer.cpp762 if (MCID.getNumDefs() != 1) in reMaterializeTrivialDef()
/external/llvm/include/llvm/CodeGen/
DMachineInstr.h323 operands_begin(), operands_begin() + getDesc().getNumDefs());
327 operands_begin(), operands_begin() + getDesc().getNumDefs());
331 operands_begin() + getDesc().getNumDefs(), operands_end());
335 operands_begin() + getDesc().getNumDefs(), operands_end());
/external/llvm/lib/Target/AArch64/
DAArch64DeadRegisterDefinitionsPass.cpp78 for (int i = 0, e = MI.getDesc().getNumDefs(); i != e; ++i) { in processMachineBasicBlock()
/external/llvm/include/llvm/MC/
DMCInstrDesc.h198 unsigned getNumDefs() const { in getNumDefs() function
/external/llvm/lib/Target/ARM/
DARMFastISel.cpp295 if (II.getNumDefs() >= 1) { in FastEmitInst_r()
320 if (II.getNumDefs() >= 1) { in FastEmitInst_rr()
350 if (II.getNumDefs() >= 1) { in FastEmitInst_rrr()
378 if (II.getNumDefs() >= 1) { in FastEmitInst_ri()
406 if (II.getNumDefs() >= 1) { in FastEmitInst_rri()
430 if (II.getNumDefs() >= 1) { in FastEmitInst_i()
DARMCodeEmitter.cpp1014 unsigned NumDefs = MCID.getNumDefs(); in emitDataProcessingInstruction()
1317 if (MCID.getNumDefs() == 2) in emitMulFrmInstruction()
DARMBaseInstrInfo.cpp3158 if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands()) in getOperandLatency()
4333 assert(MI && OpNum < MI->getDesc().getNumDefs() && "OpNum is not a def"); in breakPartialRegDependency()
/external/llvm/lib/Target/R600/
DSIISelLowering.cpp1378 unsigned NumDefs = Desc->getNumDefs(); in foldOperands()
1385 assert(!DescRev || DescRev->getNumDefs() == NumDefs); in foldOperands()
1393 assert(!DescE64 || DescE64->getNumDefs() == NumDefs); in foldOperands()
DAMDGPUISelDAGToDAG.cpp129 unsigned OpIdx = Desc.getNumDefs() + OpNo; in getOperandRegClass()
/external/llvm/lib/MC/MCParser/
DAsmParser.cpp4514 unsigned NumDefs = Desc.getNumDefs(); in parseMSInlineAsm()
/external/llvm/lib/Target/X86/
DX86FastISel.cpp1795 if (II.getNumDefs()) { in X86FastEmitCMoveSelect()

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