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Searched refs:getSubReg (Results 1 – 25 of 65) sorted by relevance

123

/external/mesa3d/src/gallium/drivers/radeon/
DR600ExpandSpecialInstrs.cpp106 Src0 = TRI.getSubReg(Src0, SubRegIndex); in runOnMachineFunction()
107 Src1 = TRI.getSubReg(Src1, SubRegIndex); in runOnMachineFunction()
112 Src1 = TRI.getSubReg(Src0, SubRegIndex1); in runOnMachineFunction()
113 Src0 = TRI.getSubReg(Src0, SubRegIndex0); in runOnMachineFunction()
120 DstReg = TRI.getSubReg(DstReg, SubRegIndex); in runOnMachineFunction()
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
DR600ExpandSpecialInstrs.cpp106 Src0 = TRI.getSubReg(Src0, SubRegIndex); in runOnMachineFunction()
107 Src1 = TRI.getSubReg(Src1, SubRegIndex); in runOnMachineFunction()
112 Src1 = TRI.getSubReg(Src0, SubRegIndex1); in runOnMachineFunction()
113 Src0 = TRI.getSubReg(Src0, SubRegIndex0); in runOnMachineFunction()
120 DstReg = TRI.getSubReg(DstReg, SubRegIndex); in runOnMachineFunction()
/external/llvm/lib/CodeGen/
DPeepholeOptimizer.cpp316 if (UseSrcSubIdx && UseMO.getSubReg() != SubIdx) in INITIALIZE_PASS_DEPENDENCY()
544 unsigned DefSubReg = MODef.getSubReg(); in optimizeCopyOrBitcast()
614 if (!MI->getOperand(0).getSubReg() && in isLoadFoldable()
791 if (Def->getOperand(DefIdx).getSubReg() != DefSubReg) in getNextSourceFromCopy()
797 SrcSubReg = Def->getOperand(SrcIdx).getSubReg(); in getNextSourceFromCopy()
812 if (Def->getOperand(DefIdx).getSubReg() != DefSubReg) in getNextSourceFromBitcast()
829 SrcSubReg = Def->getOperand(SrcIdx).getSubReg(); in getNextSourceFromBitcast()
837 if (Def->getOperand(DefIdx).getSubReg()) in getNextSourceFromRegSequence()
866 SrcSubReg = Def->getOperand(SrcIdx).getSubReg(); in getNextSourceFromRegSequence()
880 if (Def->getOperand(DefIdx).getSubReg()) in getNextSourceFromInsertSubreg()
[all …]
DCalcSpillWeights.cpp49 sub = mi->getOperand(0).getSubReg(); in copyHint()
51 hsub = mi->getOperand(1).getSubReg(); in copyHint()
53 sub = mi->getOperand(1).getSubReg(); in copyHint()
55 hsub = mi->getOperand(0).getSubReg(); in copyHint()
DTargetRegisterInfo.cpp193 if (RCI.getSubReg() == Idx) in getMatchingSuperRegClass()
232 unsigned FinalA = composeSubRegIndices(IA.getSubReg(), SubA); in getCommonSuperRegClass()
241 unsigned FinalB = composeSubRegIndices(IB.getSubReg(), SubB); in getCommonSuperRegClass()
251 *BestPreA = IA.getSubReg(); in getCommonSuperRegClass()
252 *BestPreB = IB.getSubReg(); in getCommonSuperRegClass()
DTargetInstrInfo.cpp139 unsigned SubReg0 = HasDef ? MI->getOperand(0).getSubReg() : 0; in commuteInstruction()
140 unsigned SubReg1 = MI->getOperand(Idx1).getSubReg(); in commuteInstruction()
141 unsigned SubReg2 = MI->getOperand(Idx2).getSubReg(); in commuteInstruction()
351 if (FoldOp.getSubReg() || LiveOp.getSubReg()) in canFoldCopy()
423 bool Valid = TII.getStackSlotRange(RC, MO.getSubReg(), SpillSize, in foldPatchpoint()
578 MI->getOperand(0).getSubReg() && MI->readsVirtualRegister(DefReg)) in isReallyTriviallyReMaterializableGeneric()
DOptimizePHIs.cpp110 !SrcMI->getOperand(0).getSubReg() && in IsSingleValuePHICycle()
111 !SrcMI->getOperand(1).getSubReg() && in IsSingleValuePHICycle()
DMachineInstr.cpp71 if (SubIdx && getSubReg()) in substVirtReg()
72 SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg()); in substVirtReg()
80 if (getSubReg()) { in substPhysReg()
81 Reg = TRI.getSubReg(Reg, getSubReg()); in substPhysReg()
177 getSubReg() == Other.getSubReg(); in isIdenticalTo()
219 return hash_combine(MO.getType(), MO.getReg(), MO.getSubReg(), MO.isDef()); in hash_value()
272 OS << PrintReg(getReg(), TRI, getSubReg()); in print()
288 if (isUndef() && getSubReg()) in print()
1042 if (unsigned SubIdx = MO.getSubReg()) { in getRegClassConstraintEffect()
1103 else if (MO.getSubReg() && !MO.isUndef()) in readsWritesVirtualRegister()
[all …]
DRegisterCoalescer.cpp221 DstSub = MI->getOperand(0).getSubReg(); in isMoveInstr()
223 SrcSub = MI->getOperand(1).getSubReg(); in isMoveInstr()
226 DstSub = tri.composeSubRegIndices(MI->getOperand(0).getSubReg(), in isMoveInstr()
229 SrcSub = MI->getOperand(2).getSubReg(); in isMoveInstr()
276 Dst = TRI.getSubReg(Dst, DstSub); in setRegisters()
370 Dst = TRI.getSubReg(Dst, DstSub); in isCoalescable()
375 return TRI.getSubReg(DstReg, SrcSub) == Dst; in isCoalescable()
694 UseMI->getOperand(0).getSubReg()) in removeCopyByCommutingDef()
767 if (DstOperand.getSubReg() && !DstOperand.isUndef()) in reMaterializeTrivialDef()
784 DefMI->getOperand(0).getSubReg()); in reMaterializeTrivialDef()
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DExpandPostRAPseudos.cpp88 assert(!MI->getOperand(2).getSubReg() && "SubIdx on physreg?"); in LowerSubregToReg()
92 unsigned DstSubReg = TRI->getSubReg(DstReg, SubIdx); in LowerSubregToReg()
DRegAllocFast.cpp670 if (!MO.getSubReg()) { in setPhysReg()
676 MO.setReg(PhysReg ? TRI->getSubReg(PhysReg, MO.getSubReg()) : 0); in setPhysReg()
707 (MO.getSubReg() && MI->readsVirtualRegister(Reg))) { in handleThroughOperands()
745 } else if (MO.getSubReg() && MI->readsVirtualRegister(Reg)) { in handleThroughOperands()
892 CopyDstSub = MI->getOperand(0).getSubReg(); in AllocateBasicBlock()
893 CopySrcSub = MI->getOperand(1).getSubReg(); in AllocateBasicBlock()
925 if (MO.getSubReg() && MI->readsVirtualRegister(Reg)) in AllocateBasicBlock()
DVirtRegMap.cpp345 if (MO.getSubReg()) { in rewrite()
367 PhysReg = TRI->getSubReg(PhysReg, MO.getSubReg()); in rewrite()
/external/llvm/lib/Target/R600/
DSIFixSGPRCopies.cpp151 I->getOperand(0).getSubReg())); in inferRegClassFromUses()
174 Def->getOperand(1).getSubReg()); in inferRegClassFromDef()
183 unsigned SrcSubReg = Copy.getOperand(1).getSubReg(); in isVGPRToSGPRCopy()
225 MI.getOperand(0).getSubReg()); in runOnMachineFunction()
230 MI.getOperand(0).getSubReg()); in runOnMachineFunction()
DR600ExpandSpecialInstrs.cpp186 TRI.getSubReg(DstReg, TRI.getSubRegFromChannel(Chan)), PReg); in runOnMachineFunction()
286 Src0 = TRI.getSubReg(Src0, SubRegIndex); in runOnMachineFunction()
287 Src1 = TRI.getSubReg(Src1, SubRegIndex); in runOnMachineFunction()
292 Src1 = TRI.getSubReg(Src0, SubRegIndex1); in runOnMachineFunction()
293 Src0 = TRI.getSubReg(Src0, SubRegIndex0); in runOnMachineFunction()
301 DstReg = TRI.getSubReg(DstReg, SubRegIndex); in runOnMachineFunction()
/external/llvm/lib/Target/AArch64/
DAArch64AdvSIMDScalarPass.cpp140 if (isFPR64(MI->getOperand(0).getReg(), MI->getOperand(0).getSubReg(), in getSrcFromCopy()
142 isGPR64(MI->getOperand(1).getReg(), MI->getOperand(1).getSubReg(), MRI)) in getSrcFromCopy()
144 if (isGPR64(MI->getOperand(0).getReg(), MI->getOperand(0).getSubReg(), in getSrcFromCopy()
146 isFPR64(MI->getOperand(1).getReg(), MI->getOperand(1).getSubReg(), in getSrcFromCopy()
148 SubReg = MI->getOperand(1).getSubReg(); in getSrcFromCopy()
/external/llvm/lib/Target/Sparc/
DSparcRegisterInfo.cpp179 unsigned SrcEvenReg = getSubReg(SrcReg, SP::sub_even64); in eliminateFrameIndex()
180 unsigned SrcOddReg = getSubReg(SrcReg, SP::sub_odd64); in eliminateFrameIndex()
191 unsigned DestEvenReg = getSubReg(DestReg, SP::sub_even64); in eliminateFrameIndex()
192 unsigned DestOddReg = getSubReg(DestReg, SP::sub_odd64); in eliminateFrameIndex()
/external/llvm/lib/MC/
DMCRegisterInfo.cpp21 if (RC->contains(*Supers) && Reg == getSubReg(*Supers, SubIdx)) in getMatchingSuperReg()
26 unsigned MCRegisterInfo::getSubReg(unsigned Reg, unsigned Idx) const { in getSubReg() function in MCRegisterInfo
/external/llvm/lib/Target/ARM/
DARMExpandPseudoInsts.cpp360 D0 = TRI->getSubReg(Reg, ARM::dsub_0); in GetDSubRegs()
361 D1 = TRI->getSubReg(Reg, ARM::dsub_1); in GetDSubRegs()
362 D2 = TRI->getSubReg(Reg, ARM::dsub_2); in GetDSubRegs()
363 D3 = TRI->getSubReg(Reg, ARM::dsub_3); in GetDSubRegs()
365 D0 = TRI->getSubReg(Reg, ARM::dsub_0); in GetDSubRegs()
366 D1 = TRI->getSubReg(Reg, ARM::dsub_2); in GetDSubRegs()
367 D2 = TRI->getSubReg(Reg, ARM::dsub_4); in GetDSubRegs()
368 D3 = TRI->getSubReg(Reg, ARM::dsub_6); in GetDSubRegs()
371 D0 = TRI->getSubReg(Reg, ARM::dsub_1); in GetDSubRegs()
372 D1 = TRI->getSubReg(Reg, ARM::dsub_3); in GetDSubRegs()
[all …]
/external/llvm/lib/Target/Mips/
DMipsSEFrameLowering.cpp181 unsigned Lo = RegInfo.getSubReg(Dst, Mips::sub_lo); in expandLoadACC()
182 unsigned Hi = RegInfo.getSubReg(Dst, Mips::sub_hi); in expandLoadACC()
248 unsigned DstLo = RegInfo.getSubReg(Dst, Mips::sub_lo); in expandCopyACC()
249 unsigned DstHi = RegInfo.getSubReg(Dst, Mips::sub_hi); in expandCopyACC()
330 MRI->getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_lo), true); in emitPrologue()
332 MRI->getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_hi), true); in emitPrologue()
DMipsSEInstrInfo.cpp481 unsigned DstLo = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo); in expandPseudoMTLoHi()
482 unsigned DstHi = getRegisterInfo().getSubReg(DstReg, Mips::sub_hi); in expandPseudoMTLoHi()
503 TmpReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo); in expandCvtFPInt()
506 DstReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo); in expandCvtFPInt()
522 unsigned SubReg = getRegisterInfo().getSubReg(SrcReg, SubIdx); in expandExtractElementF64()
566 BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_lo)) in expandBuildPairF64()
588 BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_hi)) in expandBuildPairF64()
/external/llvm/lib/Target/Hexagon/
DHexagonSplitConst32AndConst64.cpp142 QTM.getRegisterInfo()->getSubReg (DestReg, Hexagon::subreg_loreg); in runOnMachineFunction()
144 QTM.getRegisterInfo()->getSubReg (DestReg, Hexagon::subreg_hireg); in runOnMachineFunction()
DHexagonHardwareLoops.cpp259 unsigned getSubReg() const { in getSubReg() function in __anonf3083afd0111::CountValue
761 SR = Start->getSubReg(); in computeCount()
764 SR = End->getSubReg(); in computeCount()
779 DistSR = End->getSubReg(); in computeCount()
789 SubIB.addReg(End->getReg(), 0, End->getSubReg()) in computeCount()
790 .addReg(Start->getReg(), 0, Start->getSubReg()); in computeCount()
793 .addReg(Start->getReg(), 0, Start->getSubReg()); in computeCount()
795 SubIB.addReg(End->getReg(), 0, End->getSubReg()) in computeCount()
1084 .addReg(TripCount->getReg(), 0, TripCount->getSubReg()); in convertToHardwareLoop()
/external/llvm/lib/Target/ARM/InstPrinter/
DARMInstPrinter.cpp772 printRegName(O, MRI.getSubReg(Reg, ARM::gsub_0)); in printGPRPairOperand()
774 printRegName(O, MRI.getSubReg(Reg, ARM::gsub_1)); in printGPRPairOperand()
1321 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwo()
1322 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1); in printVectorListTwo()
1334 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwoSpaced()
1335 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2); in printVectorListTwoSpaced()
1385 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwoAllLanes()
1386 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1); in printVectorListTwoAllLanes()
1430 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwoSpacedAllLanes()
1431 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2); in printVectorListTwoSpacedAllLanes()
/external/llvm/include/llvm/CodeGen/
DMachineInstr.h727 return isCopy() && !getOperand(0).getSubReg() && !getOperand(1).getSubReg();
742 getOperand(0).getSubReg() == getOperand(1).getSubReg();
/external/llvm/lib/Target/SystemZ/
DSystemZInstrInfo.cpp63 HighRegOp.setReg(RI.getSubReg(HighRegOp.getReg(), SystemZ::subreg_h64)); in splitMove()
64 LowRegOp.setReg(RI.getSubReg(LowRegOp.getReg(), SystemZ::subreg_l64)); in splitMove()
559 copyPhysReg(MBB, MBBI, DL, RI.getSubReg(DestReg, SystemZ::subreg_h64), in copyPhysReg()
560 RI.getSubReg(SrcReg, SystemZ::subreg_h64), KillSrc); in copyPhysReg()
561 copyPhysReg(MBB, MBBI, DL, RI.getSubReg(DestReg, SystemZ::subreg_l64), in copyPhysReg()
562 RI.getSubReg(SrcReg, SystemZ::subreg_l64), KillSrc); in copyPhysReg()
710 MIB.addReg(Src.getReg(), getKillRegState(Src.isKill()), Src.getSubReg()); in convertToThreeAddress()
738 .addReg(Src.getReg(), getKillRegState(Src.isKill()), Src.getSubReg()) in convertToThreeAddress()

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