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Searched refs:isPredicated (Results 1 – 25 of 43) sorted by relevance

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/external/mesa3d/src/gallium/drivers/radeon/
DR600InstrInfo.cpp207 if(!isPredicated(LastInst)) { in AnalyzeBranch()
231 isPredicated(SecondLastInst) && in AnalyzeBranch()
233 !isPredicated(LastInst)) { in AnalyzeBranch()
314 if (isPredicated(I)) { in RemoveBranch()
332 if (isPredicated(I)) { in RemoveBranch()
343 R600InstrInfo::isPredicated(const MachineInstr *MI) const in isPredicated() function in R600InstrInfo
DR600InstrInfo.h75 bool isPredicated(const MachineInstr *MI) const;
DAMDGPUInstrInfo.h116 bool isPredicated(const MachineInstr *MI) const;
DAMDGPUInstrInfo.cpp209 bool AMDGPUInstrInfo::isPredicated(const MachineInstr *MI) const { in isPredicated() function in AMDGPUInstrInfo
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
DR600InstrInfo.cpp207 if(!isPredicated(LastInst)) { in AnalyzeBranch()
231 isPredicated(SecondLastInst) && in AnalyzeBranch()
233 !isPredicated(LastInst)) { in AnalyzeBranch()
314 if (isPredicated(I)) { in RemoveBranch()
332 if (isPredicated(I)) { in RemoveBranch()
343 R600InstrInfo::isPredicated(const MachineInstr *MI) const in isPredicated() function in R600InstrInfo
DR600InstrInfo.h75 bool isPredicated(const MachineInstr *MI) const;
DAMDGPUInstrInfo.h116 bool isPredicated(const MachineInstr *MI) const;
DAMDGPUInstrInfo.cpp209 bool AMDGPUInstrInfo::isPredicated(const MachineInstr *MI) const { in isPredicated() function in AMDGPUInstrInfo
/external/llvm/lib/Target/Hexagon/
DHexagonInstrInfo.h134 bool isPredicated(const MachineInstr *MI) const override;
135 bool isPredicated(unsigned Opcode) const;
DHexagonVLIWPacketizer.cpp466 if (!QII->isPredicated(MI)) in getPredicateSense()
600 if (QII->isPredicated(PacketMI)) { in CanPromoteToNewValueStore()
601 if (!QII->isPredicated(MI)) in CanPromoteToNewValueStore()
817 if(!QII->isPredicated(*VIN)) continue; in RestrictingDepExistInPacket()
847 assert(QII->isPredicated(MI) && "Must be predicated instruction"); in getPredicatedRegister()
1203 else if (QII->isPredicated(I) && in isLegalToPacketizeTogether()
1204 QII->isPredicated(J) && in isLegalToPacketizeTogether()
DHexagonInstrInfo.cpp150 if (isPredicated(Term) && !AnalyzeBranch(MBB, NewTBB, NewFBB, Cond, in InsertBranch()
982 bool HexagonInstrInfo::isPredicated(const MachineInstr *MI) const { in isPredicated() function in HexagonInstrInfo
988 bool HexagonInstrInfo::isPredicated(unsigned Opcode) const { in isPredicated() function in HexagonInstrInfo
997 assert(isPredicated(MI)); in isPredicatedTrue()
1014 assert(isPredicated(MI)); in isPredicatedNew()
1021 assert(isPredicated(Opcode)); in isPredicatedNew()
1525 (isPredicated(MI) && isPredicatedNew(MI))); in isDotNewInst()
1539 if (isPredicated(NewOp) && isPredicatedNew(NewOp)) { // Get predicate old form in GetDotOldOp()
DHexagonInstrInfoV5.td39 let isExtended = 1, opExtendable = 2, isPredicated = 1,
47 let isExtended = 1, opExtendable = 2, isPredicated = 1, isPredicatedFalse = 1,
539 let AddedComplexity = 100, isPredicated = 1 in
549 let AddedComplexity = 100, isPredicated = 1 in
561 let AddedComplexity = 100, isPredicated = 1 in
569 let AddedComplexity = 100, isPredicated = 1 in
577 let AddedComplexity = 100, isPredicated = 1 in
DHexagonInstrInfoV4.td261 let isPredicated = 1 in {
518 let isPredicated = 1 in {
557 let isPredicated = 1 in {
705 let opExtendable = 3, opExtentBits = 6, isPredicated = 1 in {
849 isPredicated = 1 in {
906 neverHasSideEffects = 1, isPredicated = 1 in {
965 let isPredicated = 1 in {
1066 let isPredicated = 1, isBranch = 1, isNewValue = 1, isTerminator = 1,
1126 let isPredicated = 1, isBranch = 1, isNewValue = 1, isTerminator = 1,
1184 let isPredicated = 1, isBranch = 1, isNewValue = 1, isTerminator=1,
[all …]
DHexagonInstrInfo.td123 let neverHasSideEffects = 1, isPredicated = 1 in {
151 let neverHasSideEffects = 1, isPredicated = 1 in {
202 neverHasSideEffects = 1, isPredicated = 1 in {
272 let isPredicated = 1 in {
329 let isPredicated = 1 in {
362 isPredicated = 1 in {
459 let Predicates = [HasV4T], validSubTargets = HasV4SubT, isPredicated = 1,
770 Defs = [PC], isPredicated = 1, opExtentBits = 17 in
809 let Defs = [PC], isPredicated = 1, InputType = "reg" in
935 isPredicated = 1 in {
[all …]
DHexagonInstrFormats.td115 bits<1> isPredicated = 0;
116 let TSFlags{8} = isPredicated;
185 let PredSense = !if(isPredicated, !if(isPredicatedFalse, "false", "true"),
DHexagonPeephole.cpp247 if (QII->isPredicated(MI)) { in runOnMachineFunction()
/external/llvm/lib/CodeGen/
DCriticalAntiDepBreaker.cpp173 TII->isPredicated(MI); in PrescanInstruction()
249 if (!TII->isPredicated(MI)) { in ScanInstruction()
612 if (MI->isCall() || MI->hasExtraDefRegAllocReq() || TII->isPredicated(MI)) in BreakAntiDependencies()
DIfConversion.cpp677 bool isPredicated = TII->isPredicated(I); in ScanInstructions() local
684 if (!isPredicated) { in ScanInstructions()
699 if (BBI.ClobbersPred && !isPredicated) { in ScanInstructions()
1534 if (I->isDebugValue() || TII->isPredicated(I)) in PredicateBlock()
1590 if (!TII->isPredicated(I) && !MI->isDebugValue()) { in CopyAndPredicateBlock()
DTargetSchedule.cpp272 if (!DepMI->readsRegister(Reg, TRI) && TII->isPredicated(DepMI)) in computeOutputLatency()
/external/llvm/lib/Target/R600/
DAMDGPUInstrInfo.h131 bool isPredicated(const MachineInstr *MI) const override;
DR600InstrInfo.h170 bool isPredicated(const MachineInstr *MI) const override;
DAMDGPUInstrInfo.cpp240 bool AMDGPUInstrInfo::isPredicated(const MachineInstr *MI) const { in isPredicated() function in AMDGPUInstrInfo
/external/llvm/lib/Target/PowerPC/
DPPCInstrInfo.h200 bool isPredicated(const MachineInstr *MI) const override;
/external/llvm/lib/Target/ARM/
DARMBaseInstrInfo.cpp290 while (isPredicated(I) || I->isTerminator() || I->isDebugValue()) { in AnalyzeBranch()
323 CantAnalyze = !isPredicated(I); in AnalyzeBranch()
331 if (!isPredicated(I) && in AnalyzeBranch()
441 bool ARMBaseInstrInfo::isPredicated(const MachineInstr *MI) const { in isPredicated() function in ARMBaseInstrInfo
2264 if (!isSuitableForMask(MI, SrcReg, CmpMask, false) || isPredicated(MI)) { in optimizeCompareInstr()
2272 isPredicated(PotentialAND)) in optimizeCompareInstr()
2339 if (isPredicated(MI)) in optimizeCompareInstr()
2475 assert(!isPredicated(MI) && "Can't use flags from predicated instruction"); in optimizeCompareInstr()
3975 if (MI->getOpcode() == ARM::VMOVD && !isPredicated(MI)) in getExecutionDomain()
3980 if (Subtarget.isCortexA9() && !isPredicated(MI) && in getExecutionDomain()
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/external/llvm/lib/Target/MSP430/
DMSP430InstrInfo.cpp169 return !isPredicated(MI); in isUnpredicatedTerminator()

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