/external/clang/test/CodeGen/ |
D | ppc64-vector.c | 8 typedef short v16i16 __attribute__((vector_size (32))); typedef 10 struct v16i16 { v16i16 x; }; argument 43 v16i16 test_v16i16(v16i16 x) in test_v16i16() 49 struct v16i16 test_struct_v16i16(struct v16i16 x) in test_struct_v16i16()
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/external/llvm/lib/Target/X86/ |
D | X86TargetTransformInfo.cpp | 192 { ISD::SDIV, MVT::v16i16, 6 }, // vpmulhw sequence in getArithmeticInstrCost() 193 { ISD::UDIV, MVT::v16i16, 6 }, // vpmulhuw sequence in getArithmeticInstrCost() 220 { ISD::SHL, MVT::v16i16, 16*10 }, // Scalarized. in getArithmeticInstrCost() 223 { ISD::SRL, MVT::v16i16, 8*10 }, // Scalarized. in getArithmeticInstrCost() 226 { ISD::SRA, MVT::v16i16, 16*10 }, // Scalarized. in getArithmeticInstrCost() 231 { ISD::SDIV, MVT::v16i16, 16*20 }, in getArithmeticInstrCost() 235 { ISD::UDIV, MVT::v16i16, 16*20 }, in getArithmeticInstrCost() 242 if (ISD == ISD::SHL && LT.second == MVT::v16i16 && in getArithmeticInstrCost() 356 { ISD::MUL, MVT::v16i16, 4 }, in getArithmeticInstrCost() 376 if (ISD == ISD::SHL && (VT == MVT::v8i32 || VT == MVT::v16i16) && in getArithmeticInstrCost() [all …]
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D | X86CallingConv.td | 49 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], 249 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], 271 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], 295 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], CCPassIndirect<i64>>, 419 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], 427 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
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D | X86InstrSSE.td | 341 def : Pat<(v8i16 (extract_subvector (v16i16 VR256:$src), (iPTR 0))), 342 (v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src), sub_xmm))>; 358 (INSERT_SUBREG (v16i16 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>; 415 def : Pat<(v4f64 (bitconvert (v16i16 VR256:$src))), (v4f64 VR256:$src)>; 421 def : Pat<(v8f32 (bitconvert (v16i16 VR256:$src))), (v8f32 VR256:$src)>; 426 def : Pat<(v4i64 (bitconvert (v16i16 VR256:$src))), (v4i64 VR256:$src)>; 431 def : Pat<(v32i8 (bitconvert (v16i16 VR256:$src))), (v32i8 VR256:$src)>; 433 def : Pat<(v8i32 (bitconvert (v16i16 VR256:$src))), (v8i32 VR256:$src)>; 437 def : Pat<(v16i16 (bitconvert (v8f32 VR256:$src))), (v16i16 VR256:$src)>; 438 def : Pat<(v16i16 (bitconvert (v8i32 VR256:$src))), (v16i16 VR256:$src)>; [all …]
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D | X86InstrAVX512.td | 54 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>; 60 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>; 65 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>; 70 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>; 72 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>; 76 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>; 77 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>; 78 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>; 79 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>; 80 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>; [all …]
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D | X86ISelLowering.cpp | 1138 addRegisterClass(MVT::v16i16, &X86::VR256RegClass); in resetOperationActions() 1189 setOperationAction(ISD::SRL, MVT::v16i16, Custom); in resetOperationActions() 1192 setOperationAction(ISD::SHL, MVT::v16i16, Custom); in resetOperationActions() 1195 setOperationAction(ISD::SRA, MVT::v16i16, Custom); in resetOperationActions() 1199 setOperationAction(ISD::SETCC, MVT::v16i16, Custom); in resetOperationActions() 1214 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom); in resetOperationActions() 1217 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom); in resetOperationActions() 1220 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom); in resetOperationActions() 1237 setOperationAction(ISD::ADD, MVT::v16i16, Legal); in resetOperationActions() 1242 setOperationAction(ISD::SUB, MVT::v16i16, Legal); in resetOperationActions() [all …]
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D | X86RegisterInfo.td | 438 def VR256 : RegisterClass<"X86", [v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], 463 def VR256X : RegisterClass<"X86", [v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
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D | X86InstrFragmentsSIMD.td | 480 def bc_v16i16 : PatFrag<(ops node:$in), (v16i16 (bitconvert node:$in))>;
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/external/llvm/include/llvm/CodeGen/ |
D | MachineValueType.h | 76 v16i16 = 30, // 16 x i16 enumerator 219 SimpleTy == MVT::v32i8 || SimpleTy == MVT::v16i16 || in is256BitVector() 285 case v16i16: in getVectorElementType() 323 case v16i16: in getVectorNumElements() 417 case v16i16: in getSizeInBits() 531 if (NumElements == 16) return MVT::v16i16; in getVectorVT()
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D | ValueTypes.td | 53 def v16i16 : ValueType<256, 30>; // 16 x i16 vector value
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/external/llvm/test/CodeGen/X86/ |
D | avx2-cmp.ll | 18 define <16 x i16> @v16i16-cmp(<16 x i16> %i, <16 x i16> %j) nounwind readnone { 46 define <16 x i16> @v16i16-cmpeq(<16 x i16> %i, <16 x i16> %j) nounwind readnone {
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D | avx-cmp.ll | 72 define <16 x i16> @v16i16-cmp(<16 x i16> %i, <16 x i16> %j) nounwind readnone { 116 define <16 x i16> @v16i16-cmpeq(<16 x i16> %i, <16 x i16> %j) nounwind readnone {
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D | bswap-vector.ll | 89 declare <16 x i16> @llvm.bswap.v16i16(<16 x i16>) 95 %r = call <16 x i16> @llvm.bswap.v16i16(<16 x i16> %v)
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/external/llvm/lib/Target/ARM/ |
D | ARMTargetTransformInfo.cpp | 258 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 8 }, in getCastInstrCost() 259 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i16, 8 }, in getCastInstrCost() 285 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v16f32, 8 }, in getCastInstrCost() 286 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v16f32, 8 } in getCastInstrCost() 404 { ISD::SELECT, MVT::v16i1, MVT::v16i16, 2*16 + 1 + 3*1 + 4*1 }, in getCmpSelInstrCost()
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/external/llvm/lib/Target/X86/InstPrinter/ |
D | X86InstComments.cpp | 130 DecodePSHUFHWMask(MVT::v16i16, in EmitAnyX86InstComments() 152 DecodePSHUFLWMask(MVT::v16i16, in EmitAnyX86InstComments() 191 DecodeUNPCKHMask(MVT::v16i16, ShuffleMask); in EmitAnyX86InstComments() 264 DecodeUNPCKLMask(MVT::v16i16, ShuffleMask); in EmitAnyX86InstComments()
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/external/llvm/lib/IR/ |
D | ValueTypes.cpp | 148 case MVT::v16i16: return "v16i16"; in getEVTString() 216 case MVT::v16i16: return VectorType::get(Type::getInt16Ty(Context), 16); in getTypeForEVT()
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/external/llvm/lib/Target/AArch64/ |
D | AArch64TargetTransformInfo.cpp | 451 { ISD::SELECT, MVT::v16i1, MVT::v16i16, 16 * AmortizationCost }, in getCmpSelInstrCost()
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/external/llvm/utils/TableGen/ |
D | CodeGenTarget.cpp | 89 case MVT::v16i16: return "MVT::v16i16"; in getEnumName()
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/external/llvm/test/Analysis/CostModel/X86/ |
D | vshift-cost.ll | 71 ; v16i16 and v8i32 shift left by non-uniform constant are lowered into
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/external/llvm/lib/Target/R600/ |
D | SIISelLowering.cpp | 146 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i16, Expand); in SITargetLowering() 164 setTruncStoreAction(MVT::v16i32, MVT::v16i16, Expand); in SITargetLowering()
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/external/llvm/include/llvm/IR/ |
D | Intrinsics.td | 163 def llvm_v16i16_ty : LLVMType<v16i16>; // 16 x i16
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