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Searched refs:v16i16 (Results 1 – 21 of 21) sorted by relevance

/external/clang/test/CodeGen/
Dppc64-vector.c8 typedef short v16i16 __attribute__((vector_size (32))); typedef
10 struct v16i16 { v16i16 x; }; argument
43 v16i16 test_v16i16(v16i16 x) in test_v16i16()
49 struct v16i16 test_struct_v16i16(struct v16i16 x) in test_struct_v16i16()
/external/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp192 { ISD::SDIV, MVT::v16i16, 6 }, // vpmulhw sequence in getArithmeticInstrCost()
193 { ISD::UDIV, MVT::v16i16, 6 }, // vpmulhuw sequence in getArithmeticInstrCost()
220 { ISD::SHL, MVT::v16i16, 16*10 }, // Scalarized. in getArithmeticInstrCost()
223 { ISD::SRL, MVT::v16i16, 8*10 }, // Scalarized. in getArithmeticInstrCost()
226 { ISD::SRA, MVT::v16i16, 16*10 }, // Scalarized. in getArithmeticInstrCost()
231 { ISD::SDIV, MVT::v16i16, 16*20 }, in getArithmeticInstrCost()
235 { ISD::UDIV, MVT::v16i16, 16*20 }, in getArithmeticInstrCost()
242 if (ISD == ISD::SHL && LT.second == MVT::v16i16 && in getArithmeticInstrCost()
356 { ISD::MUL, MVT::v16i16, 4 }, in getArithmeticInstrCost()
376 if (ISD == ISD::SHL && (VT == MVT::v8i32 || VT == MVT::v16i16) && in getArithmeticInstrCost()
[all …]
DX86CallingConv.td49 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
249 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
271 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
295 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], CCPassIndirect<i64>>,
419 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
427 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
DX86InstrSSE.td341 def : Pat<(v8i16 (extract_subvector (v16i16 VR256:$src), (iPTR 0))),
342 (v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src), sub_xmm))>;
358 (INSERT_SUBREG (v16i16 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
415 def : Pat<(v4f64 (bitconvert (v16i16 VR256:$src))), (v4f64 VR256:$src)>;
421 def : Pat<(v8f32 (bitconvert (v16i16 VR256:$src))), (v8f32 VR256:$src)>;
426 def : Pat<(v4i64 (bitconvert (v16i16 VR256:$src))), (v4i64 VR256:$src)>;
431 def : Pat<(v32i8 (bitconvert (v16i16 VR256:$src))), (v32i8 VR256:$src)>;
433 def : Pat<(v8i32 (bitconvert (v16i16 VR256:$src))), (v8i32 VR256:$src)>;
437 def : Pat<(v16i16 (bitconvert (v8f32 VR256:$src))), (v16i16 VR256:$src)>;
438 def : Pat<(v16i16 (bitconvert (v8i32 VR256:$src))), (v16i16 VR256:$src)>;
[all …]
DX86InstrAVX512.td54 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
60 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
65 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
70 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
72 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
76 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
77 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
78 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
79 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
80 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
[all …]
DX86ISelLowering.cpp1138 addRegisterClass(MVT::v16i16, &X86::VR256RegClass); in resetOperationActions()
1189 setOperationAction(ISD::SRL, MVT::v16i16, Custom); in resetOperationActions()
1192 setOperationAction(ISD::SHL, MVT::v16i16, Custom); in resetOperationActions()
1195 setOperationAction(ISD::SRA, MVT::v16i16, Custom); in resetOperationActions()
1199 setOperationAction(ISD::SETCC, MVT::v16i16, Custom); in resetOperationActions()
1214 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom); in resetOperationActions()
1217 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom); in resetOperationActions()
1220 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom); in resetOperationActions()
1237 setOperationAction(ISD::ADD, MVT::v16i16, Legal); in resetOperationActions()
1242 setOperationAction(ISD::SUB, MVT::v16i16, Legal); in resetOperationActions()
[all …]
DX86RegisterInfo.td438 def VR256 : RegisterClass<"X86", [v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
463 def VR256X : RegisterClass<"X86", [v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
DX86InstrFragmentsSIMD.td480 def bc_v16i16 : PatFrag<(ops node:$in), (v16i16 (bitconvert node:$in))>;
/external/llvm/include/llvm/CodeGen/
DMachineValueType.h76 v16i16 = 30, // 16 x i16 enumerator
219 SimpleTy == MVT::v32i8 || SimpleTy == MVT::v16i16 || in is256BitVector()
285 case v16i16: in getVectorElementType()
323 case v16i16: in getVectorNumElements()
417 case v16i16: in getSizeInBits()
531 if (NumElements == 16) return MVT::v16i16; in getVectorVT()
DValueTypes.td53 def v16i16 : ValueType<256, 30>; // 16 x i16 vector value
/external/llvm/test/CodeGen/X86/
Davx2-cmp.ll18 define <16 x i16> @v16i16-cmp(<16 x i16> %i, <16 x i16> %j) nounwind readnone {
46 define <16 x i16> @v16i16-cmpeq(<16 x i16> %i, <16 x i16> %j) nounwind readnone {
Davx-cmp.ll72 define <16 x i16> @v16i16-cmp(<16 x i16> %i, <16 x i16> %j) nounwind readnone {
116 define <16 x i16> @v16i16-cmpeq(<16 x i16> %i, <16 x i16> %j) nounwind readnone {
Dbswap-vector.ll89 declare <16 x i16> @llvm.bswap.v16i16(<16 x i16>)
95 %r = call <16 x i16> @llvm.bswap.v16i16(<16 x i16> %v)
/external/llvm/lib/Target/ARM/
DARMTargetTransformInfo.cpp258 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 8 }, in getCastInstrCost()
259 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i16, 8 }, in getCastInstrCost()
285 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v16f32, 8 }, in getCastInstrCost()
286 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v16f32, 8 } in getCastInstrCost()
404 { ISD::SELECT, MVT::v16i1, MVT::v16i16, 2*16 + 1 + 3*1 + 4*1 }, in getCmpSelInstrCost()
/external/llvm/lib/Target/X86/InstPrinter/
DX86InstComments.cpp130 DecodePSHUFHWMask(MVT::v16i16, in EmitAnyX86InstComments()
152 DecodePSHUFLWMask(MVT::v16i16, in EmitAnyX86InstComments()
191 DecodeUNPCKHMask(MVT::v16i16, ShuffleMask); in EmitAnyX86InstComments()
264 DecodeUNPCKLMask(MVT::v16i16, ShuffleMask); in EmitAnyX86InstComments()
/external/llvm/lib/IR/
DValueTypes.cpp148 case MVT::v16i16: return "v16i16"; in getEVTString()
216 case MVT::v16i16: return VectorType::get(Type::getInt16Ty(Context), 16); in getTypeForEVT()
/external/llvm/lib/Target/AArch64/
DAArch64TargetTransformInfo.cpp451 { ISD::SELECT, MVT::v16i1, MVT::v16i16, 16 * AmortizationCost }, in getCmpSelInstrCost()
/external/llvm/utils/TableGen/
DCodeGenTarget.cpp89 case MVT::v16i16: return "MVT::v16i16"; in getEnumName()
/external/llvm/test/Analysis/CostModel/X86/
Dvshift-cost.ll71 ; v16i16 and v8i32 shift left by non-uniform constant are lowered into
/external/llvm/lib/Target/R600/
DSIISelLowering.cpp146 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i16, Expand); in SITargetLowering()
164 setTruncStoreAction(MVT::v16i32, MVT::v16i16, Expand); in SITargetLowering()
/external/llvm/include/llvm/IR/
DIntrinsics.td163 def llvm_v16i16_ty : LLVMType<v16i16>; // 16 x i16