Searched refs:VectorList (Results 1 – 4 of 4) sorted by relevance
| /external/eigen/unsupported/Eigen/src/IterativeSolvers/ |
| D | IncompleteCholesky.h | 40 typedef std::vector<std::list<Index> > VectorList; typedef
127 …wIdx, SclType& vals, const Index& col, const Index& jk, IndexType& firstElt, VectorList& listCol);
152 VectorList listCol(n); // listCol(j) is a linked list of columns to update column j in factorize()
241 …rowIdx, SclType& vals, const Index& col, const Index& jk, IndexType& firstElt, VectorList& listCol) in updateList()
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| /external/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 522 struct VectorListOp VectorList; member
562 VectorList = o.VectorList; in ARMOperand()
1391 return Kind == k_VectorList && !VectorList.isDoubleSpaced; in isSingleSpacedVectorList()
1394 return Kind == k_VectorList && VectorList.isDoubleSpaced; in isDoubleSpacedVectorList()
1398 return VectorList.Count == 1; in isVecListOneD()
1404 .contains(VectorList.RegNum)); in isVecListDPair()
1409 return VectorList.Count == 3; in isVecListThreeD()
1414 return VectorList.Count == 4; in isVecListFourD()
1421 .contains(VectorList.RegNum)); in isVecListDPairSpaced()
1426 return VectorList.Count == 3; in isVecListThreeQ()
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| /external/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 238 struct VectorListOp VectorList; member
286 VectorList = o.VectorList; in AArch64Operand()
358 return VectorList.RegNum; in getVectorListStart()
363 return VectorList.Count; in getVectorListCount()
900 return Kind == k_VectorList && VectorList.Count == NumRegs && in isImplicitlyTypedVectorList()
901 !VectorList.ElementKind; in isImplicitlyTypedVectorList()
908 if (VectorList.Count != NumRegs) in isTypedVectorList()
910 if (VectorList.ElementKind != ElementKind) in isTypedVectorList()
912 return VectorList.NumElements == NumElements; in isTypedVectorList()
1601 Op->VectorList.RegNum = RegNum; in CreateVectorList()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64RegisterInfo.td | 482 multiclass VectorList<int count, RegisterClass Reg64, RegisterClass Reg128> {
583 defm VecListOne : VectorList<1, FPR64, FPR128>;
584 defm VecListTwo : VectorList<2, DD, QQ>;
585 defm VecListThree : VectorList<3, DDD, QQQ>;
586 defm VecListFour : VectorList<4, DDDD, QQQQ>;
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