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Searched refs:reg3 (Results 1 – 25 of 45) sorted by relevance

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/external/llvm/test/CodeGen/ARM/
Dfast-isel-pic.ll30 ; ARMv7-ELF: ldr r[[reg3:[0-9]+]],
31 ; ARMv7-ELF: ldr r[[reg2]], [r[[reg3]], r[[reg2]]]
41 ; THUMB: movw r[[reg3:[0-9]+]],
42 ; THUMB: movt r[[reg3]],
43 ; THUMB: add r[[reg3]], pc
44 ; THUMB: ldr r[[reg3]], [r[[reg3]]]
46 ; THUMB-ELF: ldr r[[reg3:[0-9]+]],
48 ; THUMB-ELF: ldr r[[reg3]], [r[[reg3]], r[[reg4]]]
/external/linux-tools-perf/perf-3.12.0/arch/arm/lib/
Dmemcpy.S23 .macro ldr4w ptr reg1 reg2 reg3 reg4 abort
24 ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4}
27 .macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
28 ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
39 .macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
40 stmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
/external/llvm/test/CodeGen/R600/
Dpv-packing.ll6 …float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2, <4 x float> inreg %reg3) #0 {
14 %6 = extractelement <4 x float> %reg3, i32 0
15 %7 = extractelement <4 x float> %reg3, i32 1
16 %8 = extractelement <4 x float> %reg3, i32 2
Dload-input-fold.ll4 …float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2, <4 x float> inreg %reg3) #0 {
14 %8 = extractelement <4 x float> %reg3, i32 0
15 %9 = extractelement <4 x float> %reg3, i32 1
16 %10 = extractelement <4 x float> %reg3, i32 2
17 %11 = extractelement <4 x float> %reg3, i32 3
Dpv.ll6 …eg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2, <4 x float> inreg %reg3, <4 x float> inreg …
16 %8 = extractelement <4 x float> %reg3, i32 0
17 %9 = extractelement <4 x float> %reg3, i32 1
18 %10 = extractelement <4 x float> %reg3, i32 2
19 %11 = extractelement <4 x float> %reg3, i32 3
Dbig_alu.ll7 …eg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2, <4 x float> inreg %reg3, <4 x float> inreg …
35 %26 = extractelement <4 x float> %reg3, i32 0
36 %27 = extractelement <4 x float> %reg3, i32 1
37 %28 = extractelement <4 x float> %reg3, i32 2
38 %29 = extractelement <4 x float> %reg3, i32 3
/external/valgrind/main/none/tests/s390x/
Dcksm.c27 register uint64_t reg3 asm("3") = len; in cksm_by_insn()
33 : "+d" (sum), "+d" (reg2), "+d" (reg3) : : "cc", "memory"); in cksm_by_insn()
36 len = reg3; in cksm_by_insn()
/external/vixl/src/a64/
Dmacro-assembler-a64.cc1416 const Register& reg3, in Include() argument
1418 RegList include = reg1.Bit() | reg2.Bit() | reg3.Bit() | reg4.Bit(); in Include()
1428 const FPRegister& reg3, in Include() argument
1430 RegList include = reg1.Bit() | reg2.Bit() | reg3.Bit() | reg4.Bit(); in Include()
1447 const Register& reg3, in Exclude() argument
1449 RegList exclude = reg1.Bit() | reg2.Bit() | reg3.Bit() | reg4.Bit(); in Exclude()
1456 const FPRegister& reg3, in Exclude() argument
1458 RegList excludefp = reg1.Bit() | reg2.Bit() | reg3.Bit() | reg4.Bit(); in Exclude()
1465 const CPURegister& reg3, in Exclude() argument
1470 const CPURegister regs[] = {reg1, reg2, reg3, reg4}; in Exclude()
Dmacro-assembler-a64.h1321 const Register& reg3 = NoReg,
1325 const FPRegister& reg3 = NoFPReg,
1335 const Register& reg3 = NoReg,
1339 const FPRegister& reg3 = NoFPReg,
1343 const CPURegister& reg3 = NoCPUReg,
Dassembler-a64.h283 const CPURegister& reg3 = NoReg,
297 const CPURegister& reg3 = NoCPUReg,
310 CPURegister reg3 = NoCPUReg,
312 : list_(reg1.Bit() | reg2.Bit() | reg3.Bit() | reg4.Bit()),
314 VIXL_ASSERT(AreSameSizeAndType(reg1, reg2, reg3, reg4));
Dassembler-a64.cc2246 const CPURegister& reg3, const CPURegister& reg4, in AreAliased() argument
2255 const CPURegister regs[] = {reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8}; in AreAliased()
2283 const CPURegister& reg3, const CPURegister& reg4, in AreSameSizeAndType() argument
2289 match &= !reg3.IsValid() || reg3.IsSameSizeAndType(reg1); in AreSameSizeAndType()
/external/pixman/pixman/
Dpixman-arm-neon-asm.h92 .macro pixldst4 op, elem_size, reg1, reg2, reg3, reg4, mem_operand, abits
94 op&.&elem_size {d&reg1, d&reg2, d&reg3, d&reg4}, [&mem_operand&, :&abits&]!
96 op&.&elem_size {d&reg1, d&reg2, d&reg3, d&reg4}, [&mem_operand&]!
104 .macro pixldst3 op, elem_size, reg1, reg2, reg3, mem_operand
105 op&.&elem_size {d&reg1, d&reg2, d&reg3}, [&mem_operand&]!
108 .macro pixldst30 op, elem_size, reg1, reg2, reg3, idx, mem_operand
109 op&.&elem_size {d&reg1[idx], d&reg2[idx], d&reg3[idx]}, [&mem_operand&]!
Dpixman-android-neon.S93 acc1, acc2, reg1, reg2, reg3, reg4, tmp1, tmp2
98 bilinear_load_8888 reg3, reg4, tmp2
99 vmull.u8 acc2, reg3, d28
Dpixman-arm-simd-asm.h99 .macro pixldst op, cond=al, numbytes, reg0, reg1, reg2, reg3, base, unaligned=0
105 op&r&cond WK&reg3, [base], #4
107 op&m&cond&ia base!, {WK&reg0,WK&reg1,WK&reg2,WK&reg3}
127 .macro pixst_baseupdated cond, numbytes, reg0, reg1, reg2, reg3, base
129 stm&cond&db base, {WK&reg0,WK&reg1,WK&reg2,WK&reg3}
Dpixman-arm-neon-asm-bilinear.S109 acc1, acc2, reg1, reg2, reg3, reg4, tmp1, tmp2
114 bilinear_load_8888 reg3, reg4, tmp2
115 vmull.u8 acc2, reg3, d28
130 acc1, acc2, reg1, reg2, reg3, reg4, acc2lo, acc2hi
142 convert_0565_to_x888 acc2, reg3, reg2, reg1
143 vzip.u8 reg1, reg3
145 vzip.u8 reg3, reg4
149 vmull.u8 acc2, reg3, d28
Dpixman-arm-simd-asm.S374 .macro over_8888_8888_check_transparent numbytes, reg0, reg1, reg2, reg3 argument
381 teqeq WK&reg3, #0
Dpixman-arm-neon-asm.S2868 acc1, acc2, reg1, reg2, reg3, reg4, tmp1, tmp2
2873 bilinear_load_8888 reg3, reg4, tmp2
2874 vmull.u8 acc2, reg3, d28
2889 acc1, acc2, reg1, reg2, reg3, reg4, acc2lo, acc2hi
2901 convert_0565_to_x888 acc2, reg3, reg2, reg1
2902 vzip.u8 reg1, reg3
2904 vzip.u8 reg3, reg4
2908 vmull.u8 acc2, reg3, d28
/external/chromium_org/third_party/skia/gm/
Dglyph_pos.cpp198 static GMRegistry reg3(GlyphPosHairlineStrokeFactory);
Dbitmaprect.cpp254 static skiagm::GMRegistry reg3(MyFactory3);
Dgradients.cpp450 static GMRegistry reg3(MyFactory3);
/external/chromium_org/third_party/sqlite/src/src/
Dbuild.c865 int reg1, reg2, reg3; in sqlite3StartTable() local
879 reg3 = ++pParse->nMem; in sqlite3StartTable()
880 sqlite3VdbeAddOp3(v, OP_ReadCookie, iDb, reg3, BTREE_FILE_FORMAT); in sqlite3StartTable()
882 j1 = sqlite3VdbeAddOp1(v, OP_If, reg3); in sqlite3StartTable()
885 sqlite3VdbeAddOp2(v, OP_Integer, fileFormat, reg3); in sqlite3StartTable()
886 sqlite3VdbeAddOp3(v, OP_SetCookie, iDb, BTREE_FILE_FORMAT, reg3); in sqlite3StartTable()
887 sqlite3VdbeAddOp2(v, OP_Integer, ENC(db), reg3); in sqlite3StartTable()
888 sqlite3VdbeAddOp3(v, OP_SetCookie, iDb, BTREE_TEXT_ENCODING, reg3); in sqlite3StartTable()
910 sqlite3VdbeAddOp2(v, OP_Null, 0, reg3); in sqlite3StartTable()
911 sqlite3VdbeAddOp3(v, OP_Insert, 0, reg3, reg1); in sqlite3StartTable()
/external/skia/gm/
Dbitmaprect.cpp247 static skiagm::GMRegistry reg3(MyFactory3);
Dgradients.cpp454 static GMRegistry reg3(MyFactory3);
/external/chromium_org/v8/src/arm64/
Dassembler-arm64.h412 Register reg3 = NoReg,
420 const CPURegister& reg3 = NoReg,
433 const CPURegister& reg3 = NoCPUReg,
450 CPURegister reg3 = NoCPUReg,
452 : list_(reg1.Bit() | reg2.Bit() | reg3.Bit() | reg4.Bit()),
454 DCHECK(AreSameSizeAndType(reg1, reg2, reg3, reg4));
Dassembler-arm64.cc207 Register reg3, Register reg4) { in GetAllocatableRegisterThatIsNotOneOf() argument
208 CPURegList regs(reg1, reg2, reg3, reg4); in GetAllocatableRegisterThatIsNotOneOf()
220 const CPURegister& reg3, const CPURegister& reg4, in AreAliased() argument
229 const CPURegister regs[] = {reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8}; in AreAliased()
257 const CPURegister& reg3, const CPURegister& reg4, in AreSameSizeAndType() argument
263 match &= !reg3.IsValid() || reg3.IsSameSizeAndType(reg1); in AreSameSizeAndType()

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