1 //===-- RegisterClassInfo.cpp - Dynamic Register Class Info ---------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the RegisterClassInfo class which provides dynamic
11 // information about target register classes. Callee-saved vs. caller-saved and
12 // reserved registers depend on calling conventions and other dynamic
13 // information, so some things cannot be determined statically.
14 //
15 //===----------------------------------------------------------------------===//
16
17 #include "llvm/CodeGen/RegisterClassInfo.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/Support/CommandLine.h"
21 #include "llvm/Support/Debug.h"
22 #include "llvm/Support/raw_ostream.h"
23 #include "llvm/Target/TargetMachine.h"
24
25 using namespace llvm;
26
27 #define DEBUG_TYPE "regalloc"
28
29 static cl::opt<unsigned>
30 StressRA("stress-regalloc", cl::Hidden, cl::init(0), cl::value_desc("N"),
31 cl::desc("Limit all regclasses to N registers"));
32
RegisterClassInfo()33 RegisterClassInfo::RegisterClassInfo()
34 : Tag(0), MF(nullptr), TRI(nullptr), CalleeSaved(nullptr) {}
35
runOnMachineFunction(const MachineFunction & mf)36 void RegisterClassInfo::runOnMachineFunction(const MachineFunction &mf) {
37 bool Update = false;
38 MF = &mf;
39
40 // Allocate new array the first time we see a new target.
41 if (MF->getTarget().getRegisterInfo() != TRI) {
42 TRI = MF->getTarget().getRegisterInfo();
43 RegClass.reset(new RCInfo[TRI->getNumRegClasses()]);
44 unsigned NumPSets = TRI->getNumRegPressureSets();
45 PSetLimits.reset(new unsigned[NumPSets]);
46 std::fill(&PSetLimits[0], &PSetLimits[NumPSets], 0);
47 Update = true;
48 }
49
50 // Does this MF have different CSRs?
51 const MCPhysReg *CSR = TRI->getCalleeSavedRegs(MF);
52 if (Update || CSR != CalleeSaved) {
53 // Build a CSRNum map. Every CSR alias gets an entry pointing to the last
54 // overlapping CSR.
55 CSRNum.clear();
56 CSRNum.resize(TRI->getNumRegs(), 0);
57 for (unsigned N = 0; unsigned Reg = CSR[N]; ++N)
58 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
59 CSRNum[*AI] = N + 1; // 0 means no CSR, 1 means CalleeSaved[0], ...
60 Update = true;
61 }
62 CalleeSaved = CSR;
63
64 // Different reserved registers?
65 const BitVector &RR = MF->getRegInfo().getReservedRegs();
66 if (Reserved.size() != RR.size() || RR != Reserved) {
67 Update = true;
68 Reserved = RR;
69 }
70
71 // Invalidate cached information from previous function.
72 if (Update)
73 ++Tag;
74 }
75
76 /// compute - Compute the preferred allocation order for RC with reserved
77 /// registers filtered out. Volatile registers come first followed by CSR
78 /// aliases ordered according to the CSR order specified by the target.
compute(const TargetRegisterClass * RC) const79 void RegisterClassInfo::compute(const TargetRegisterClass *RC) const {
80 RCInfo &RCI = RegClass[RC->getID()];
81
82 // Raw register count, including all reserved regs.
83 unsigned NumRegs = RC->getNumRegs();
84
85 if (!RCI.Order)
86 RCI.Order.reset(new MCPhysReg[NumRegs]);
87
88 unsigned N = 0;
89 SmallVector<MCPhysReg, 16> CSRAlias;
90 unsigned MinCost = 0xff;
91 unsigned LastCost = ~0u;
92 unsigned LastCostChange = 0;
93
94 // FIXME: Once targets reserve registers instead of removing them from the
95 // allocation order, we can simply use begin/end here.
96 ArrayRef<MCPhysReg> RawOrder = RC->getRawAllocationOrder(*MF);
97 for (unsigned i = 0; i != RawOrder.size(); ++i) {
98 unsigned PhysReg = RawOrder[i];
99 // Remove reserved registers from the allocation order.
100 if (Reserved.test(PhysReg))
101 continue;
102 unsigned Cost = TRI->getCostPerUse(PhysReg);
103 MinCost = std::min(MinCost, Cost);
104
105 if (CSRNum[PhysReg])
106 // PhysReg aliases a CSR, save it for later.
107 CSRAlias.push_back(PhysReg);
108 else {
109 if (Cost != LastCost)
110 LastCostChange = N;
111 RCI.Order[N++] = PhysReg;
112 LastCost = Cost;
113 }
114 }
115 RCI.NumRegs = N + CSRAlias.size();
116 assert (RCI.NumRegs <= NumRegs && "Allocation order larger than regclass");
117
118 // CSR aliases go after the volatile registers, preserve the target's order.
119 for (unsigned i = 0, e = CSRAlias.size(); i != e; ++i) {
120 unsigned PhysReg = CSRAlias[i];
121 unsigned Cost = TRI->getCostPerUse(PhysReg);
122 if (Cost != LastCost)
123 LastCostChange = N;
124 RCI.Order[N++] = PhysReg;
125 LastCost = Cost;
126 }
127
128 // Register allocator stress test. Clip register class to N registers.
129 if (StressRA && RCI.NumRegs > StressRA)
130 RCI.NumRegs = StressRA;
131
132 // Check if RC is a proper sub-class.
133 if (const TargetRegisterClass *Super = TRI->getLargestLegalSuperClass(RC))
134 if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs)
135 RCI.ProperSubClass = true;
136
137 RCI.MinCost = uint8_t(MinCost);
138 RCI.LastCostChange = LastCostChange;
139
140 DEBUG({
141 dbgs() << "AllocationOrder(" << RC->getName() << ") = [";
142 for (unsigned I = 0; I != RCI.NumRegs; ++I)
143 dbgs() << ' ' << PrintReg(RCI.Order[I], TRI);
144 dbgs() << (RCI.ProperSubClass ? " ] (sub-class)\n" : " ]\n");
145 });
146
147 // RCI is now up-to-date.
148 RCI.Tag = Tag;
149 }
150
151 /// This is not accurate because two overlapping register sets may have some
152 /// nonoverlapping reserved registers. However, computing the allocation order
153 /// for all register classes would be too expensive.
computePSetLimit(unsigned Idx) const154 unsigned RegisterClassInfo::computePSetLimit(unsigned Idx) const {
155 const TargetRegisterClass *RC = nullptr;
156 unsigned NumRCUnits = 0;
157 for (TargetRegisterInfo::regclass_iterator
158 RI = TRI->regclass_begin(), RE = TRI->regclass_end(); RI != RE; ++RI) {
159 const int *PSetID = TRI->getRegClassPressureSets(*RI);
160 for (; *PSetID != -1; ++PSetID) {
161 if ((unsigned)*PSetID == Idx)
162 break;
163 }
164 if (*PSetID == -1)
165 continue;
166
167 // Found a register class that counts against this pressure set.
168 // For efficiency, only compute the set order for the largest set.
169 unsigned NUnits = TRI->getRegClassWeight(*RI).WeightLimit;
170 if (!RC || NUnits > NumRCUnits) {
171 RC = *RI;
172 NumRCUnits = NUnits;
173 }
174 }
175 compute(RC);
176 unsigned NReserved = RC->getNumRegs() - getNumAllocatableRegs(RC);
177 return TRI->getRegPressureSetLimit(Idx)
178 - TRI->getRegClassWeight(RC).RegWeight * NReserved;
179 }
180