1 //===-- Host.cpp - Implement OS Host Concept --------------------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the operating system Host concept.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "llvm/Support/Host.h"
15 #include "llvm/ADT/SmallVector.h"
16 #include "llvm/ADT/StringRef.h"
17 #include "llvm/ADT/StringSwitch.h"
18 #include "llvm/ADT/Triple.h"
19 #include "llvm/Config/config.h"
20 #include "llvm/Support/DataStream.h"
21 #include "llvm/Support/Debug.h"
22 #include "llvm/Support/raw_ostream.h"
23 #include <string.h>
24
25 // Include the platform-specific parts of this class.
26 #ifdef LLVM_ON_UNIX
27 #include "Unix/Host.inc"
28 #endif
29 #ifdef LLVM_ON_WIN32
30 #include "Windows/Host.inc"
31 #endif
32 #ifdef _MSC_VER
33 #include <intrin.h>
34 #endif
35 #if defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__))
36 #include <mach/mach.h>
37 #include <mach/mach_host.h>
38 #include <mach/host_info.h>
39 #include <mach/machine.h>
40 #endif
41
42 #define DEBUG_TYPE "host-detection"
43
44 //===----------------------------------------------------------------------===//
45 //
46 // Implementations of the CPU detection routines
47 //
48 //===----------------------------------------------------------------------===//
49
50 using namespace llvm;
51
52 #if defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)\
53 || defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
54
55 /// GetX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in the
56 /// specified arguments. If we can't run cpuid on the host, return true.
GetX86CpuIDAndInfo(unsigned value,unsigned * rEAX,unsigned * rEBX,unsigned * rECX,unsigned * rEDX)57 static bool GetX86CpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX,
58 unsigned *rECX, unsigned *rEDX) {
59 #if defined(__GNUC__) || defined(__clang__)
60 #if defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
61 // gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually.
62 asm ("movq\t%%rbx, %%rsi\n\t"
63 "cpuid\n\t"
64 "xchgq\t%%rbx, %%rsi\n\t"
65 : "=a" (*rEAX),
66 "=S" (*rEBX),
67 "=c" (*rECX),
68 "=d" (*rEDX)
69 : "a" (value));
70 return false;
71 #elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
72 asm ("movl\t%%ebx, %%esi\n\t"
73 "cpuid\n\t"
74 "xchgl\t%%ebx, %%esi\n\t"
75 : "=a" (*rEAX),
76 "=S" (*rEBX),
77 "=c" (*rECX),
78 "=d" (*rEDX)
79 : "a" (value));
80 return false;
81 // pedantic #else returns to appease -Wunreachable-code (so we don't generate
82 // postprocessed code that looks like "return true; return false;")
83 #else
84 return true;
85 #endif
86 #elif defined(_MSC_VER)
87 // The MSVC intrinsic is portable across x86 and x64.
88 int registers[4];
89 __cpuid(registers, value);
90 *rEAX = registers[0];
91 *rEBX = registers[1];
92 *rECX = registers[2];
93 *rEDX = registers[3];
94 return false;
95 #else
96 return true;
97 #endif
98 }
99
100 /// GetX86CpuIDAndInfoEx - Execute the specified cpuid with subleaf and return the
101 /// 4 values in the specified arguments. If we can't run cpuid on the host,
102 /// return true.
GetX86CpuIDAndInfoEx(unsigned value,unsigned subleaf,unsigned * rEAX,unsigned * rEBX,unsigned * rECX,unsigned * rEDX)103 static bool GetX86CpuIDAndInfoEx(unsigned value, unsigned subleaf,
104 unsigned *rEAX, unsigned *rEBX, unsigned *rECX,
105 unsigned *rEDX) {
106 #if defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
107 #if defined(__GNUC__)
108 // gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually.
109 asm ("movq\t%%rbx, %%rsi\n\t"
110 "cpuid\n\t"
111 "xchgq\t%%rbx, %%rsi\n\t"
112 : "=a" (*rEAX),
113 "=S" (*rEBX),
114 "=c" (*rECX),
115 "=d" (*rEDX)
116 : "a" (value),
117 "c" (subleaf));
118 return false;
119 #elif defined(_MSC_VER)
120 // __cpuidex was added in MSVC++ 9.0 SP1
121 #if (_MSC_VER > 1500) || (_MSC_VER == 1500 && _MSC_FULL_VER >= 150030729)
122 int registers[4];
123 __cpuidex(registers, value, subleaf);
124 *rEAX = registers[0];
125 *rEBX = registers[1];
126 *rECX = registers[2];
127 *rEDX = registers[3];
128 return false;
129 #else
130 return true;
131 #endif
132 #else
133 return true;
134 #endif
135 #elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
136 #if defined(__GNUC__)
137 asm ("movl\t%%ebx, %%esi\n\t"
138 "cpuid\n\t"
139 "xchgl\t%%ebx, %%esi\n\t"
140 : "=a" (*rEAX),
141 "=S" (*rEBX),
142 "=c" (*rECX),
143 "=d" (*rEDX)
144 : "a" (value),
145 "c" (subleaf));
146 return false;
147 #elif defined(_MSC_VER)
148 __asm {
149 mov eax,value
150 mov ecx,subleaf
151 cpuid
152 mov esi,rEAX
153 mov dword ptr [esi],eax
154 mov esi,rEBX
155 mov dword ptr [esi],ebx
156 mov esi,rECX
157 mov dword ptr [esi],ecx
158 mov esi,rEDX
159 mov dword ptr [esi],edx
160 }
161 return false;
162 #else
163 return true;
164 #endif
165 #else
166 return true;
167 #endif
168 }
169
OSHasAVXSupport()170 static bool OSHasAVXSupport() {
171 #if defined(__GNUC__)
172 // Check xgetbv; this uses a .byte sequence instead of the instruction
173 // directly because older assemblers do not include support for xgetbv and
174 // there is no easy way to conditionally compile based on the assembler used.
175 int rEAX, rEDX;
176 __asm__ (".byte 0x0f, 0x01, 0xd0" : "=a" (rEAX), "=d" (rEDX) : "c" (0));
177 #elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK)
178 unsigned long long rEAX = _xgetbv(_XCR_XFEATURE_ENABLED_MASK);
179 #else
180 int rEAX = 0; // Ensures we return false
181 #endif
182 return (rEAX & 6) == 6;
183 }
184
DetectX86FamilyModel(unsigned EAX,unsigned & Family,unsigned & Model)185 static void DetectX86FamilyModel(unsigned EAX, unsigned &Family,
186 unsigned &Model) {
187 Family = (EAX >> 8) & 0xf; // Bits 8 - 11
188 Model = (EAX >> 4) & 0xf; // Bits 4 - 7
189 if (Family == 6 || Family == 0xf) {
190 if (Family == 0xf)
191 // Examine extended family ID if family ID is F.
192 Family += (EAX >> 20) & 0xff; // Bits 20 - 27
193 // Examine extended model ID if family ID is 6 or F.
194 Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19
195 }
196 }
197
getHostCPUName()198 StringRef sys::getHostCPUName() {
199 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
200 if (GetX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX))
201 return "generic";
202 unsigned Family = 0;
203 unsigned Model = 0;
204 DetectX86FamilyModel(EAX, Family, Model);
205
206 union {
207 unsigned u[3];
208 char c[12];
209 } text;
210
211 GetX86CpuIDAndInfo(0, &EAX, text.u+0, text.u+2, text.u+1);
212
213 unsigned MaxLeaf = EAX;
214 bool HasSSE3 = (ECX & 0x1);
215 bool HasSSE41 = (ECX & 0x80000);
216 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV
217 // indicates that the AVX registers will be saved and restored on context
218 // switch, then we have full AVX support.
219 const unsigned AVXBits = (1 << 27) | (1 << 28);
220 bool HasAVX = ((ECX & AVXBits) == AVXBits) && OSHasAVXSupport();
221 bool HasAVX2 = HasAVX && MaxLeaf >= 0x7 &&
222 !GetX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX) &&
223 (EBX & 0x20);
224 GetX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
225 bool Em64T = (EDX >> 29) & 0x1;
226 bool HasTBM = (ECX >> 21) & 0x1;
227
228 if (memcmp(text.c, "GenuineIntel", 12) == 0) {
229 switch (Family) {
230 case 3:
231 return "i386";
232 case 4:
233 switch (Model) {
234 case 0: // Intel486 DX processors
235 case 1: // Intel486 DX processors
236 case 2: // Intel486 SX processors
237 case 3: // Intel487 processors, IntelDX2 OverDrive processors,
238 // IntelDX2 processors
239 case 4: // Intel486 SL processor
240 case 5: // IntelSX2 processors
241 case 7: // Write-Back Enhanced IntelDX2 processors
242 case 8: // IntelDX4 OverDrive processors, IntelDX4 processors
243 default: return "i486";
244 }
245 case 5:
246 switch (Model) {
247 case 1: // Pentium OverDrive processor for Pentium processor (60, 66),
248 // Pentium processors (60, 66)
249 case 2: // Pentium OverDrive processor for Pentium processor (75, 90,
250 // 100, 120, 133), Pentium processors (75, 90, 100, 120, 133,
251 // 150, 166, 200)
252 case 3: // Pentium OverDrive processors for Intel486 processor-based
253 // systems
254 return "pentium";
255
256 case 4: // Pentium OverDrive processor with MMX technology for Pentium
257 // processor (75, 90, 100, 120, 133), Pentium processor with
258 // MMX technology (166, 200)
259 return "pentium-mmx";
260
261 default: return "pentium";
262 }
263 case 6:
264 switch (Model) {
265 case 1: // Pentium Pro processor
266 return "pentiumpro";
267
268 case 3: // Intel Pentium II OverDrive processor, Pentium II processor,
269 // model 03
270 case 5: // Pentium II processor, model 05, Pentium II Xeon processor,
271 // model 05, and Intel Celeron processor, model 05
272 case 6: // Celeron processor, model 06
273 return "pentium2";
274
275 case 7: // Pentium III processor, model 07, and Pentium III Xeon
276 // processor, model 07
277 case 8: // Pentium III processor, model 08, Pentium III Xeon processor,
278 // model 08, and Celeron processor, model 08
279 case 10: // Pentium III Xeon processor, model 0Ah
280 case 11: // Pentium III processor, model 0Bh
281 return "pentium3";
282
283 case 9: // Intel Pentium M processor, Intel Celeron M processor model 09.
284 case 13: // Intel Pentium M processor, Intel Celeron M processor, model
285 // 0Dh. All processors are manufactured using the 90 nm process.
286 return "pentium-m";
287
288 case 14: // Intel Core Duo processor, Intel Core Solo processor, model
289 // 0Eh. All processors are manufactured using the 65 nm process.
290 return "yonah";
291
292 case 15: // Intel Core 2 Duo processor, Intel Core 2 Duo mobile
293 // processor, Intel Core 2 Quad processor, Intel Core 2 Quad
294 // mobile processor, Intel Core 2 Extreme processor, Intel
295 // Pentium Dual-Core processor, Intel Xeon processor, model
296 // 0Fh. All processors are manufactured using the 65 nm process.
297 case 22: // Intel Celeron processor model 16h. All processors are
298 // manufactured using the 65 nm process
299 return "core2";
300
301 case 21: // Intel EP80579 Integrated Processor and Intel EP80579
302 // Integrated Processor with Intel QuickAssist Technology
303 return "i686"; // FIXME: ???
304
305 case 23: // Intel Core 2 Extreme processor, Intel Xeon processor, model
306 // 17h. All processors are manufactured using the 45 nm process.
307 //
308 // 45nm: Penryn , Wolfdale, Yorkfield (XE)
309 // Not all Penryn processors support SSE 4.1 (such as the Pentium brand)
310 return HasSSE41 ? "penryn" : "core2";
311
312 case 26: // Intel Core i7 processor and Intel Xeon processor. All
313 // processors are manufactured using the 45 nm process.
314 case 29: // Intel Xeon processor MP. All processors are manufactured using
315 // the 45 nm process.
316 case 30: // Intel(R) Core(TM) i7 CPU 870 @ 2.93GHz.
317 // As found in a Summer 2010 model iMac.
318 case 37: // Intel Core i7, laptop version.
319 case 44: // Intel Core i7 processor and Intel Xeon processor. All
320 // processors are manufactured using the 32 nm process.
321 case 46: // Nehalem EX
322 case 47: // Westmere EX
323 return "corei7";
324
325 // SandyBridge:
326 case 42: // Intel Core i7 processor. All processors are manufactured
327 // using the 32 nm process.
328 case 45:
329 // Not all Sandy Bridge processors support AVX (such as the Pentium
330 // versions instead of the i7 versions).
331 return HasAVX ? "corei7-avx" : "corei7";
332
333 // Ivy Bridge:
334 case 58:
335 case 62: // Ivy Bridge EP
336 // Not all Ivy Bridge processors support AVX (such as the Pentium
337 // versions instead of the i7 versions).
338 return HasAVX ? "core-avx-i" : "corei7";
339
340 // Haswell:
341 case 60:
342 case 63:
343 case 69:
344 case 70:
345 // Not all Haswell processors support AVX too (such as the Pentium
346 // versions instead of the i7 versions).
347 return HasAVX2 ? "core-avx2" : "corei7";
348
349 case 28: // Most 45 nm Intel Atom processors
350 case 38: // 45 nm Atom Lincroft
351 case 39: // 32 nm Atom Medfield
352 case 53: // 32 nm Atom Midview
353 case 54: // 32 nm Atom Midview
354 return "atom";
355
356 // Atom Silvermont codes from the Intel software optimization guide.
357 case 55:
358 case 74:
359 case 77:
360 return "slm";
361
362 default: return (Em64T) ? "x86-64" : "i686";
363 }
364 case 15: {
365 switch (Model) {
366 case 0: // Pentium 4 processor, Intel Xeon processor. All processors are
367 // model 00h and manufactured using the 0.18 micron process.
368 case 1: // Pentium 4 processor, Intel Xeon processor, Intel Xeon
369 // processor MP, and Intel Celeron processor. All processors are
370 // model 01h and manufactured using the 0.18 micron process.
371 case 2: // Pentium 4 processor, Mobile Intel Pentium 4 processor - M,
372 // Intel Xeon processor, Intel Xeon processor MP, Intel Celeron
373 // processor, and Mobile Intel Celeron processor. All processors
374 // are model 02h and manufactured using the 0.13 micron process.
375 return (Em64T) ? "x86-64" : "pentium4";
376
377 case 3: // Pentium 4 processor, Intel Xeon processor, Intel Celeron D
378 // processor. All processors are model 03h and manufactured using
379 // the 90 nm process.
380 case 4: // Pentium 4 processor, Pentium 4 processor Extreme Edition,
381 // Pentium D processor, Intel Xeon processor, Intel Xeon
382 // processor MP, Intel Celeron D processor. All processors are
383 // model 04h and manufactured using the 90 nm process.
384 case 6: // Pentium 4 processor, Pentium D processor, Pentium processor
385 // Extreme Edition, Intel Xeon processor, Intel Xeon processor
386 // MP, Intel Celeron D processor. All processors are model 06h
387 // and manufactured using the 65 nm process.
388 return (Em64T) ? "nocona" : "prescott";
389
390 default:
391 return (Em64T) ? "x86-64" : "pentium4";
392 }
393 }
394
395 default:
396 return "generic";
397 }
398 } else if (memcmp(text.c, "AuthenticAMD", 12) == 0) {
399 // FIXME: this poorly matches the generated SubtargetFeatureKV table. There
400 // appears to be no way to generate the wide variety of AMD-specific targets
401 // from the information returned from CPUID.
402 switch (Family) {
403 case 4:
404 return "i486";
405 case 5:
406 switch (Model) {
407 case 6:
408 case 7: return "k6";
409 case 8: return "k6-2";
410 case 9:
411 case 13: return "k6-3";
412 case 10: return "geode";
413 default: return "pentium";
414 }
415 case 6:
416 switch (Model) {
417 case 4: return "athlon-tbird";
418 case 6:
419 case 7:
420 case 8: return "athlon-mp";
421 case 10: return "athlon-xp";
422 default: return "athlon";
423 }
424 case 15:
425 if (HasSSE3)
426 return "k8-sse3";
427 switch (Model) {
428 case 1: return "opteron";
429 case 5: return "athlon-fx"; // also opteron
430 default: return "athlon64";
431 }
432 case 16:
433 return "amdfam10";
434 case 20:
435 return "btver1";
436 case 21:
437 if (!HasAVX) // If the OS doesn't support AVX provide a sane fallback.
438 return "btver1";
439 if (Model >= 0x50)
440 return "bdver4"; // 50h-6Fh: Excavator
441 if (Model >= 0x30)
442 return "bdver3"; // 30h-3Fh: Steamroller
443 if (Model >= 0x10 || HasTBM)
444 return "bdver2"; // 10h-1Fh: Piledriver
445 return "bdver1"; // 00h-0Fh: Bulldozer
446 case 22:
447 if (!HasAVX) // If the OS doesn't support AVX provide a sane fallback.
448 return "btver1";
449 return "btver2";
450 default:
451 return "generic";
452 }
453 }
454 return "generic";
455 }
456 #elif defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__))
getHostCPUName()457 StringRef sys::getHostCPUName() {
458 host_basic_info_data_t hostInfo;
459 mach_msg_type_number_t infoCount;
460
461 infoCount = HOST_BASIC_INFO_COUNT;
462 host_info(mach_host_self(), HOST_BASIC_INFO, (host_info_t)&hostInfo,
463 &infoCount);
464
465 if (hostInfo.cpu_type != CPU_TYPE_POWERPC) return "generic";
466
467 switch(hostInfo.cpu_subtype) {
468 case CPU_SUBTYPE_POWERPC_601: return "601";
469 case CPU_SUBTYPE_POWERPC_602: return "602";
470 case CPU_SUBTYPE_POWERPC_603: return "603";
471 case CPU_SUBTYPE_POWERPC_603e: return "603e";
472 case CPU_SUBTYPE_POWERPC_603ev: return "603ev";
473 case CPU_SUBTYPE_POWERPC_604: return "604";
474 case CPU_SUBTYPE_POWERPC_604e: return "604e";
475 case CPU_SUBTYPE_POWERPC_620: return "620";
476 case CPU_SUBTYPE_POWERPC_750: return "750";
477 case CPU_SUBTYPE_POWERPC_7400: return "7400";
478 case CPU_SUBTYPE_POWERPC_7450: return "7450";
479 case CPU_SUBTYPE_POWERPC_970: return "970";
480 default: ;
481 }
482
483 return "generic";
484 }
485 #elif defined(__linux__) && (defined(__ppc__) || defined(__powerpc__))
getHostCPUName()486 StringRef sys::getHostCPUName() {
487 // Access to the Processor Version Register (PVR) on PowerPC is privileged,
488 // and so we must use an operating-system interface to determine the current
489 // processor type. On Linux, this is exposed through the /proc/cpuinfo file.
490 const char *generic = "generic";
491
492 // Note: We cannot mmap /proc/cpuinfo here and then process the resulting
493 // memory buffer because the 'file' has 0 size (it can be read from only
494 // as a stream).
495
496 std::string Err;
497 DataStreamer *DS = getDataFileStreamer("/proc/cpuinfo", &Err);
498 if (!DS) {
499 DEBUG(dbgs() << "Unable to open /proc/cpuinfo: " << Err << "\n");
500 return generic;
501 }
502
503 // The cpu line is second (after the 'processor: 0' line), so if this
504 // buffer is too small then something has changed (or is wrong).
505 char buffer[1024];
506 size_t CPUInfoSize = DS->GetBytes((unsigned char*) buffer, sizeof(buffer));
507 delete DS;
508
509 const char *CPUInfoStart = buffer;
510 const char *CPUInfoEnd = buffer + CPUInfoSize;
511
512 const char *CIP = CPUInfoStart;
513
514 const char *CPUStart = 0;
515 size_t CPULen = 0;
516
517 // We need to find the first line which starts with cpu, spaces, and a colon.
518 // After the colon, there may be some additional spaces and then the cpu type.
519 while (CIP < CPUInfoEnd && CPUStart == 0) {
520 if (CIP < CPUInfoEnd && *CIP == '\n')
521 ++CIP;
522
523 if (CIP < CPUInfoEnd && *CIP == 'c') {
524 ++CIP;
525 if (CIP < CPUInfoEnd && *CIP == 'p') {
526 ++CIP;
527 if (CIP < CPUInfoEnd && *CIP == 'u') {
528 ++CIP;
529 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t'))
530 ++CIP;
531
532 if (CIP < CPUInfoEnd && *CIP == ':') {
533 ++CIP;
534 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t'))
535 ++CIP;
536
537 if (CIP < CPUInfoEnd) {
538 CPUStart = CIP;
539 while (CIP < CPUInfoEnd && (*CIP != ' ' && *CIP != '\t' &&
540 *CIP != ',' && *CIP != '\n'))
541 ++CIP;
542 CPULen = CIP - CPUStart;
543 }
544 }
545 }
546 }
547 }
548
549 if (CPUStart == 0)
550 while (CIP < CPUInfoEnd && *CIP != '\n')
551 ++CIP;
552 }
553
554 if (CPUStart == 0)
555 return generic;
556
557 return StringSwitch<const char *>(StringRef(CPUStart, CPULen))
558 .Case("604e", "604e")
559 .Case("604", "604")
560 .Case("7400", "7400")
561 .Case("7410", "7400")
562 .Case("7447", "7400")
563 .Case("7455", "7450")
564 .Case("G4", "g4")
565 .Case("POWER4", "970")
566 .Case("PPC970FX", "970")
567 .Case("PPC970MP", "970")
568 .Case("G5", "g5")
569 .Case("POWER5", "g5")
570 .Case("A2", "a2")
571 .Case("POWER6", "pwr6")
572 .Case("POWER7", "pwr7")
573 .Case("POWER8", "pwr8")
574 .Case("POWER8E", "pwr8")
575 .Default(generic);
576 }
577 #elif defined(__linux__) && defined(__arm__)
getHostCPUName()578 StringRef sys::getHostCPUName() {
579 // The cpuid register on arm is not accessible from user space. On Linux,
580 // it is exposed through the /proc/cpuinfo file.
581 // Note: We cannot mmap /proc/cpuinfo here and then process the resulting
582 // memory buffer because the 'file' has 0 size (it can be read from only
583 // as a stream).
584
585 std::string Err;
586 DataStreamer *DS = getDataFileStreamer("/proc/cpuinfo", &Err);
587 if (!DS) {
588 DEBUG(dbgs() << "Unable to open /proc/cpuinfo: " << Err << "\n");
589 return "generic";
590 }
591
592 // Read 1024 bytes from /proc/cpuinfo, which should contain the CPU part line
593 // in all cases.
594 char buffer[1024];
595 size_t CPUInfoSize = DS->GetBytes((unsigned char*) buffer, sizeof(buffer));
596 delete DS;
597
598 StringRef Str(buffer, CPUInfoSize);
599
600 SmallVector<StringRef, 32> Lines;
601 Str.split(Lines, "\n");
602
603 // Look for the CPU implementer line.
604 StringRef Implementer;
605 for (unsigned I = 0, E = Lines.size(); I != E; ++I)
606 if (Lines[I].startswith("CPU implementer"))
607 Implementer = Lines[I].substr(15).ltrim("\t :");
608
609 if (Implementer == "0x41") // ARM Ltd.
610 // Look for the CPU part line.
611 for (unsigned I = 0, E = Lines.size(); I != E; ++I)
612 if (Lines[I].startswith("CPU part"))
613 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The
614 // values correspond to the "Part number" in the CP15/c0 register. The
615 // contents are specified in the various processor manuals.
616 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :"))
617 .Case("0x926", "arm926ej-s")
618 .Case("0xb02", "mpcore")
619 .Case("0xb36", "arm1136j-s")
620 .Case("0xb56", "arm1156t2-s")
621 .Case("0xb76", "arm1176jz-s")
622 .Case("0xc08", "cortex-a8")
623 .Case("0xc09", "cortex-a9")
624 .Case("0xc0f", "cortex-a15")
625 .Case("0xc20", "cortex-m0")
626 .Case("0xc23", "cortex-m3")
627 .Case("0xc24", "cortex-m4")
628 .Default("generic");
629
630 if (Implementer == "0x51") // Qualcomm Technologies, Inc.
631 // Look for the CPU part line.
632 for (unsigned I = 0, E = Lines.size(); I != E; ++I)
633 if (Lines[I].startswith("CPU part"))
634 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The
635 // values correspond to the "Part number" in the CP15/c0 register. The
636 // contents are specified in the various processor manuals.
637 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :"))
638 .Case("0x06f", "krait") // APQ8064
639 .Default("generic");
640
641 return "generic";
642 }
643 #elif defined(__linux__) && defined(__s390x__)
getHostCPUName()644 StringRef sys::getHostCPUName() {
645 // STIDP is a privileged operation, so use /proc/cpuinfo instead.
646 // Note: We cannot mmap /proc/cpuinfo here and then process the resulting
647 // memory buffer because the 'file' has 0 size (it can be read from only
648 // as a stream).
649
650 std::string Err;
651 DataStreamer *DS = getDataFileStreamer("/proc/cpuinfo", &Err);
652 if (!DS) {
653 DEBUG(dbgs() << "Unable to open /proc/cpuinfo: " << Err << "\n");
654 return "generic";
655 }
656
657 // The "processor 0:" line comes after a fair amount of other information,
658 // including a cache breakdown, but this should be plenty.
659 char buffer[2048];
660 size_t CPUInfoSize = DS->GetBytes((unsigned char*) buffer, sizeof(buffer));
661 delete DS;
662
663 StringRef Str(buffer, CPUInfoSize);
664 SmallVector<StringRef, 32> Lines;
665 Str.split(Lines, "\n");
666 for (unsigned I = 0, E = Lines.size(); I != E; ++I) {
667 if (Lines[I].startswith("processor ")) {
668 size_t Pos = Lines[I].find("machine = ");
669 if (Pos != StringRef::npos) {
670 Pos += sizeof("machine = ") - 1;
671 unsigned int Id;
672 if (!Lines[I].drop_front(Pos).getAsInteger(10, Id)) {
673 if (Id >= 2827)
674 return "zEC12";
675 if (Id >= 2817)
676 return "z196";
677 }
678 }
679 break;
680 }
681 }
682
683 return "generic";
684 }
685 #else
getHostCPUName()686 StringRef sys::getHostCPUName() {
687 return "generic";
688 }
689 #endif
690
691 #if defined(__linux__) && (defined(__arm__) || defined(__aarch64__))
getHostCPUFeatures(StringMap<bool> & Features)692 bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
693 std::string Err;
694 DataStreamer *DS = getDataFileStreamer("/proc/cpuinfo", &Err);
695 if (!DS) {
696 DEBUG(dbgs() << "Unable to open /proc/cpuinfo: " << Err << "\n");
697 return false;
698 }
699
700 // Read 1024 bytes from /proc/cpuinfo, which should contain the Features line
701 // in all cases.
702 char buffer[1024];
703 size_t CPUInfoSize = DS->GetBytes((unsigned char*) buffer, sizeof(buffer));
704 delete DS;
705
706 StringRef Str(buffer, CPUInfoSize);
707
708 SmallVector<StringRef, 32> Lines;
709 Str.split(Lines, "\n");
710
711 SmallVector<StringRef, 32> CPUFeatures;
712
713 // Look for the CPU features.
714 for (unsigned I = 0, E = Lines.size(); I != E; ++I)
715 if (Lines[I].startswith("Features")) {
716 Lines[I].split(CPUFeatures, " ");
717 break;
718 }
719
720 #if defined(__aarch64__)
721 // Keep track of which crypto features we have seen
722 enum {
723 CAP_AES = 0x1,
724 CAP_PMULL = 0x2,
725 CAP_SHA1 = 0x4,
726 CAP_SHA2 = 0x8
727 };
728 uint32_t crypto = 0;
729 #endif
730
731 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) {
732 StringRef LLVMFeatureStr = StringSwitch<StringRef>(CPUFeatures[I])
733 #if defined(__aarch64__)
734 .Case("asimd", "neon")
735 .Case("fp", "fp-armv8")
736 .Case("crc32", "crc")
737 #else
738 .Case("half", "fp16")
739 .Case("neon", "neon")
740 .Case("vfpv3", "vfp3")
741 .Case("vfpv3d16", "d16")
742 .Case("vfpv4", "vfp4")
743 .Case("idiva", "hwdiv-arm")
744 .Case("idivt", "hwdiv")
745 #endif
746 .Default("");
747
748 #if defined(__aarch64__)
749 // We need to check crypto separately since we need all of the crypto
750 // extensions to enable the subtarget feature
751 if (CPUFeatures[I] == "aes")
752 crypto |= CAP_AES;
753 else if (CPUFeatures[I] == "pmull")
754 crypto |= CAP_PMULL;
755 else if (CPUFeatures[I] == "sha1")
756 crypto |= CAP_SHA1;
757 else if (CPUFeatures[I] == "sha2")
758 crypto |= CAP_SHA2;
759 #endif
760
761 if (LLVMFeatureStr != "")
762 Features.GetOrCreateValue(LLVMFeatureStr).setValue(true);
763 }
764
765 #if defined(__aarch64__)
766 // If we have all crypto bits we can add the feature
767 if (crypto == (CAP_AES | CAP_PMULL | CAP_SHA1 | CAP_SHA2))
768 Features.GetOrCreateValue("crypto").setValue(true);
769 #endif
770
771 return true;
772 }
773 #else
getHostCPUFeatures(StringMap<bool> & Features)774 bool sys::getHostCPUFeatures(StringMap<bool> &Features){
775 return false;
776 }
777 #endif
778
getProcessTriple()779 std::string sys::getProcessTriple() {
780 Triple PT(Triple::normalize(LLVM_HOST_TRIPLE));
781
782 if (sizeof(void *) == 8 && PT.isArch32Bit())
783 PT = PT.get64BitArchVariant();
784 if (sizeof(void *) == 4 && PT.isArch64Bit())
785 PT = PT.get32BitArchVariant();
786
787 return PT.str();
788 }
789