1 //===-- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon -------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Implements the info about Hexagon target spec.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "HexagonTargetMachine.h"
15 #include "Hexagon.h"
16 #include "HexagonISelLowering.h"
17 #include "HexagonMachineScheduler.h"
18 #include "HexagonTargetObjectFile.h"
19 #include "llvm/CodeGen/Passes.h"
20 #include "llvm/IR/Module.h"
21 #include "llvm/PassManager.h"
22 #include "llvm/Support/CommandLine.h"
23 #include "llvm/Support/TargetRegistry.h"
24 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
25 #include "llvm/Transforms/Scalar.h"
26
27 using namespace llvm;
28
29 static cl:: opt<bool> DisableHardwareLoops("disable-hexagon-hwloops",
30 cl::Hidden, cl::desc("Disable Hardware Loops for Hexagon target"));
31
32 static cl::opt<bool> DisableHexagonMISched("disable-hexagon-misched",
33 cl::Hidden, cl::ZeroOrMore, cl::init(false),
34 cl::desc("Disable Hexagon MI Scheduling"));
35
36 static cl::opt<bool> DisableHexagonCFGOpt("disable-hexagon-cfgopt",
37 cl::Hidden, cl::ZeroOrMore, cl::init(false),
38 cl::desc("Disable Hexagon CFG Optimization"));
39
40
41 /// HexagonTargetMachineModule - Note that this is used on hosts that
42 /// cannot link in a library unless there are references into the
43 /// library. In particular, it seems that it is not possible to get
44 /// things to work on Win32 without this. Though it is unused, do not
45 /// remove it.
46 extern "C" int HexagonTargetMachineModule;
47 int HexagonTargetMachineModule = 0;
48
LLVMInitializeHexagonTarget()49 extern "C" void LLVMInitializeHexagonTarget() {
50 // Register the target.
51 RegisterTargetMachine<HexagonTargetMachine> X(TheHexagonTarget);
52 }
53
createVLIWMachineSched(MachineSchedContext * C)54 static ScheduleDAGInstrs *createVLIWMachineSched(MachineSchedContext *C) {
55 return new VLIWMachineScheduler(C, make_unique<ConvergingVLIWScheduler>());
56 }
57
58 static MachineSchedRegistry
59 SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler",
60 createVLIWMachineSched);
61
62 /// HexagonTargetMachine ctor - Create an ILP32 architecture model.
63 ///
64
65 /// Hexagon_TODO: Do I need an aggregate alignment?
66 ///
HexagonTargetMachine(const Target & T,StringRef TT,StringRef CPU,StringRef FS,const TargetOptions & Options,Reloc::Model RM,CodeModel::Model CM,CodeGenOpt::Level OL)67 HexagonTargetMachine::HexagonTargetMachine(const Target &T, StringRef TT,
68 StringRef CPU, StringRef FS,
69 const TargetOptions &Options,
70 Reloc::Model RM, CodeModel::Model CM,
71 CodeGenOpt::Level OL)
72 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
73 Subtarget(TT, CPU, FS, *this) {
74 initAsmInfo();
75 }
76
77 namespace {
78 /// Hexagon Code Generator Pass Configuration Options.
79 class HexagonPassConfig : public TargetPassConfig {
80 public:
HexagonPassConfig(HexagonTargetMachine * TM,PassManagerBase & PM)81 HexagonPassConfig(HexagonTargetMachine *TM, PassManagerBase &PM)
82 : TargetPassConfig(TM, PM) {
83 // FIXME: Rather than calling enablePass(&MachineSchedulerID) below, define
84 // HexagonSubtarget::enableMachineScheduler() { return true; }.
85 // That will bypass the SelectionDAG VLIW scheduler, which is probably just
86 // hurting compile time and will be removed eventually anyway.
87 if (DisableHexagonMISched)
88 disablePass(&MachineSchedulerID);
89 else
90 enablePass(&MachineSchedulerID);
91 }
92
getHexagonTargetMachine() const93 HexagonTargetMachine &getHexagonTargetMachine() const {
94 return getTM<HexagonTargetMachine>();
95 }
96
97 ScheduleDAGInstrs *
createMachineScheduler(MachineSchedContext * C) const98 createMachineScheduler(MachineSchedContext *C) const override {
99 return createVLIWMachineSched(C);
100 }
101
102 bool addInstSelector() override;
103 bool addPreRegAlloc() override;
104 bool addPostRegAlloc() override;
105 bool addPreSched2() override;
106 bool addPreEmitPass() override;
107 };
108 } // namespace
109
createPassConfig(PassManagerBase & PM)110 TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM) {
111 return new HexagonPassConfig(this, PM);
112 }
113
addInstSelector()114 bool HexagonPassConfig::addInstSelector() {
115 HexagonTargetMachine &TM = getHexagonTargetMachine();
116 bool NoOpt = (getOptLevel() == CodeGenOpt::None);
117
118 if (!NoOpt)
119 addPass(createHexagonRemoveExtendArgs(TM));
120
121 addPass(createHexagonISelDag(TM, getOptLevel()));
122
123 if (!NoOpt) {
124 addPass(createHexagonPeephole());
125 printAndVerify("After hexagon peephole pass");
126 }
127
128 return false;
129 }
130
addPreRegAlloc()131 bool HexagonPassConfig::addPreRegAlloc() {
132 if (getOptLevel() != CodeGenOpt::None)
133 if (!DisableHardwareLoops)
134 addPass(createHexagonHardwareLoops());
135 return false;
136 }
137
addPostRegAlloc()138 bool HexagonPassConfig::addPostRegAlloc() {
139 const HexagonTargetMachine &TM = getHexagonTargetMachine();
140 if (getOptLevel() != CodeGenOpt::None)
141 if (!DisableHexagonCFGOpt)
142 addPass(createHexagonCFGOptimizer(TM));
143 return false;
144 }
145
addPreSched2()146 bool HexagonPassConfig::addPreSched2() {
147 const HexagonTargetMachine &TM = getHexagonTargetMachine();
148
149 addPass(createHexagonCopyToCombine());
150 if (getOptLevel() != CodeGenOpt::None)
151 addPass(&IfConverterID);
152 addPass(createHexagonSplitConst32AndConst64(TM));
153 printAndVerify("After hexagon split const32/64 pass");
154 return true;
155 }
156
addPreEmitPass()157 bool HexagonPassConfig::addPreEmitPass() {
158 const HexagonTargetMachine &TM = getHexagonTargetMachine();
159 bool NoOpt = (getOptLevel() == CodeGenOpt::None);
160
161 if (!NoOpt)
162 addPass(createHexagonNewValueJump());
163
164 // Expand Spill code for predicate registers.
165 addPass(createHexagonExpandPredSpillCode(TM));
166
167 // Split up TFRcondsets into conditional transfers.
168 addPass(createHexagonSplitTFRCondSets(TM));
169
170 // Create Packets.
171 if (!NoOpt) {
172 if (!DisableHardwareLoops)
173 addPass(createHexagonFixupHwLoops());
174 addPass(createHexagonPacketizer());
175 }
176
177 return false;
178 }
179