1 //===-- MipsAsmBackend.cpp - Mips Asm Backend ----------------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the MipsAsmBackend class.
11 //
12 //===----------------------------------------------------------------------===//
13 //
14
15 #include "MCTargetDesc/MipsFixupKinds.h"
16 #include "MCTargetDesc/MipsAsmBackend.h"
17 #include "MCTargetDesc/MipsMCTargetDesc.h"
18 #include "llvm/MC/MCAsmBackend.h"
19 #include "llvm/MC/MCAssembler.h"
20 #include "llvm/MC/MCContext.h"
21 #include "llvm/MC/MCDirectives.h"
22 #include "llvm/MC/MCELFObjectWriter.h"
23 #include "llvm/MC/MCFixupKindInfo.h"
24 #include "llvm/MC/MCObjectWriter.h"
25 #include "llvm/MC/MCSubtargetInfo.h"
26 #include "llvm/Support/ErrorHandling.h"
27 #include "llvm/Support/MathExtras.h"
28 #include "llvm/Support/raw_ostream.h"
29
30 using namespace llvm;
31
32 // Prepare value for the target space for it
adjustFixupValue(const MCFixup & Fixup,uint64_t Value,MCContext * Ctx=nullptr)33 static unsigned adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
34 MCContext *Ctx = nullptr) {
35
36 unsigned Kind = Fixup.getKind();
37
38 // Add/subtract and shift
39 switch (Kind) {
40 default:
41 return 0;
42 case FK_Data_2:
43 case FK_GPRel_4:
44 case FK_Data_4:
45 case FK_Data_8:
46 case Mips::fixup_Mips_LO16:
47 case Mips::fixup_Mips_GPREL16:
48 case Mips::fixup_Mips_GPOFF_HI:
49 case Mips::fixup_Mips_GPOFF_LO:
50 case Mips::fixup_Mips_GOT_PAGE:
51 case Mips::fixup_Mips_GOT_OFST:
52 case Mips::fixup_Mips_GOT_DISP:
53 case Mips::fixup_Mips_GOT_LO16:
54 case Mips::fixup_Mips_CALL_LO16:
55 case Mips::fixup_MICROMIPS_LO16:
56 case Mips::fixup_MICROMIPS_GOT_PAGE:
57 case Mips::fixup_MICROMIPS_GOT_OFST:
58 case Mips::fixup_MICROMIPS_GOT_DISP:
59 case Mips::fixup_MIPS_PCLO16:
60 break;
61 case Mips::fixup_Mips_PC16:
62 // So far we are only using this type for branches.
63 // For branches we start 1 instruction after the branch
64 // so the displacement will be one instruction size less.
65 Value -= 4;
66 // The displacement is then divided by 4 to give us an 18 bit
67 // address range. Forcing a signed division because Value can be negative.
68 Value = (int64_t)Value / 4;
69 // We now check if Value can be encoded as a 16-bit signed immediate.
70 if (!isIntN(16, Value) && Ctx)
71 Ctx->FatalError(Fixup.getLoc(), "out of range PC16 fixup");
72 break;
73 case Mips::fixup_MIPS_PC19_S2:
74 // Forcing a signed division because Value can be negative.
75 Value = (int64_t)Value / 4;
76 // We now check if Value can be encoded as a 19-bit signed immediate.
77 if (!isIntN(19, Value) && Ctx)
78 Ctx->FatalError(Fixup.getLoc(), "out of range PC19 fixup");
79 break;
80 case Mips::fixup_Mips_26:
81 // So far we are only using this type for jumps.
82 // The displacement is then divided by 4 to give us an 28 bit
83 // address range.
84 Value >>= 2;
85 break;
86 case Mips::fixup_Mips_HI16:
87 case Mips::fixup_Mips_GOT_Local:
88 case Mips::fixup_Mips_GOT_HI16:
89 case Mips::fixup_Mips_CALL_HI16:
90 case Mips::fixup_MICROMIPS_HI16:
91 case Mips::fixup_MIPS_PCHI16:
92 // Get the 2nd 16-bits. Also add 1 if bit 15 is 1.
93 Value = ((Value + 0x8000) >> 16) & 0xffff;
94 break;
95 case Mips::fixup_Mips_HIGHER:
96 // Get the 3rd 16-bits.
97 Value = ((Value + 0x80008000LL) >> 32) & 0xffff;
98 break;
99 case Mips::fixup_Mips_HIGHEST:
100 // Get the 4th 16-bits.
101 Value = ((Value + 0x800080008000LL) >> 48) & 0xffff;
102 break;
103 case Mips::fixup_MICROMIPS_26_S1:
104 Value >>= 1;
105 break;
106 case Mips::fixup_MICROMIPS_PC16_S1:
107 Value -= 4;
108 // Forcing a signed division because Value can be negative.
109 Value = (int64_t)Value / 2;
110 // We now check if Value can be encoded as a 16-bit signed immediate.
111 if (!isIntN(16, Value) && Ctx)
112 Ctx->FatalError(Fixup.getLoc(), "out of range PC16 fixup");
113 break;
114 case Mips::fixup_MIPS_PC18_S3:
115 // Forcing a signed division because Value can be negative.
116 Value = (int64_t)Value / 8;
117 // We now check if Value can be encoded as a 18-bit signed immediate.
118 if (!isIntN(18, Value) && Ctx)
119 Ctx->FatalError(Fixup.getLoc(), "out of range PC18 fixup");
120 break;
121 case Mips::fixup_MIPS_PC21_S2:
122 Value -= 4;
123 // Forcing a signed division because Value can be negative.
124 Value = (int64_t) Value / 4;
125 // We now check if Value can be encoded as a 21-bit signed immediate.
126 if (!isIntN(21, Value) && Ctx)
127 Ctx->FatalError(Fixup.getLoc(), "out of range PC21 fixup");
128 break;
129 case Mips::fixup_MIPS_PC26_S2:
130 Value -= 4;
131 // Forcing a signed division because Value can be negative.
132 Value = (int64_t) Value / 4;
133 // We now check if Value can be encoded as a 26-bit signed immediate.
134 if (!isIntN(26, Value) && Ctx)
135 Ctx->FatalError(Fixup.getLoc(), "out of range PC26 fixup");
136 break;
137 }
138
139 return Value;
140 }
141
createObjectWriter(raw_ostream & OS) const142 MCObjectWriter *MipsAsmBackend::createObjectWriter(raw_ostream &OS) const {
143 return createMipsELFObjectWriter(OS,
144 MCELFObjectTargetWriter::getOSABI(OSType), IsLittle, Is64Bit);
145 }
146
147 // Little-endian fixup data byte ordering:
148 // mips32r2: a | b | x | x
149 // microMIPS: x | x | a | b
150
needsMMLEByteOrder(unsigned Kind)151 static bool needsMMLEByteOrder(unsigned Kind) {
152 return Kind >= Mips::fixup_MICROMIPS_26_S1 &&
153 Kind < Mips::LastTargetFixupKind;
154 }
155
156 // Calculate index for microMIPS specific little endian byte order
calculateMMLEIndex(unsigned i)157 static unsigned calculateMMLEIndex(unsigned i) {
158 assert(i <= 3 && "Index out of range!");
159
160 return (1 - i / 2) * 2 + i % 2;
161 }
162
163 /// ApplyFixup - Apply the \p Value for given \p Fixup into the provided
164 /// data fragment, at the offset specified by the fixup and following the
165 /// fixup kind as appropriate.
applyFixup(const MCFixup & Fixup,char * Data,unsigned DataSize,uint64_t Value,bool IsPCRel) const166 void MipsAsmBackend::applyFixup(const MCFixup &Fixup, char *Data,
167 unsigned DataSize, uint64_t Value,
168 bool IsPCRel) const {
169 MCFixupKind Kind = Fixup.getKind();
170 Value = adjustFixupValue(Fixup, Value);
171
172 if (!Value)
173 return; // Doesn't change encoding.
174
175 // Where do we start in the object
176 unsigned Offset = Fixup.getOffset();
177 // Number of bytes we need to fixup
178 unsigned NumBytes = (getFixupKindInfo(Kind).TargetSize + 7) / 8;
179 // Used to point to big endian bytes
180 unsigned FullSize;
181
182 switch ((unsigned)Kind) {
183 case FK_Data_2:
184 case Mips::fixup_Mips_16:
185 FullSize = 2;
186 break;
187 case FK_Data_8:
188 case Mips::fixup_Mips_64:
189 FullSize = 8;
190 break;
191 case FK_Data_4:
192 default:
193 FullSize = 4;
194 break;
195 }
196
197 // Grab current value, if any, from bits.
198 uint64_t CurVal = 0;
199
200 bool microMipsLEByteOrder = needsMMLEByteOrder((unsigned) Kind);
201
202 for (unsigned i = 0; i != NumBytes; ++i) {
203 unsigned Idx = IsLittle ? (microMipsLEByteOrder ? calculateMMLEIndex(i)
204 : i)
205 : (FullSize - 1 - i);
206 CurVal |= (uint64_t)((uint8_t)Data[Offset + Idx]) << (i*8);
207 }
208
209 uint64_t Mask = ((uint64_t)(-1) >>
210 (64 - getFixupKindInfo(Kind).TargetSize));
211 CurVal |= Value & Mask;
212
213 // Write out the fixed up bytes back to the code/data bits.
214 for (unsigned i = 0; i != NumBytes; ++i) {
215 unsigned Idx = IsLittle ? (microMipsLEByteOrder ? calculateMMLEIndex(i)
216 : i)
217 : (FullSize - 1 - i);
218 Data[Offset + Idx] = (uint8_t)((CurVal >> (i*8)) & 0xff);
219 }
220 }
221
222 const MCFixupKindInfo &MipsAsmBackend::
getFixupKindInfo(MCFixupKind Kind) const223 getFixupKindInfo(MCFixupKind Kind) const {
224 const static MCFixupKindInfo LittleEndianInfos[Mips::NumTargetFixupKinds] = {
225 // This table *must* be in same the order of fixup_* kinds in
226 // MipsFixupKinds.h.
227 //
228 // name offset bits flags
229 { "fixup_Mips_16", 0, 16, 0 },
230 { "fixup_Mips_32", 0, 32, 0 },
231 { "fixup_Mips_REL32", 0, 32, 0 },
232 { "fixup_Mips_26", 0, 26, 0 },
233 { "fixup_Mips_HI16", 0, 16, 0 },
234 { "fixup_Mips_LO16", 0, 16, 0 },
235 { "fixup_Mips_GPREL16", 0, 16, 0 },
236 { "fixup_Mips_LITERAL", 0, 16, 0 },
237 { "fixup_Mips_GOT_Global", 0, 16, 0 },
238 { "fixup_Mips_GOT_Local", 0, 16, 0 },
239 { "fixup_Mips_PC16", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
240 { "fixup_Mips_CALL16", 0, 16, 0 },
241 { "fixup_Mips_GPREL32", 0, 32, 0 },
242 { "fixup_Mips_SHIFT5", 6, 5, 0 },
243 { "fixup_Mips_SHIFT6", 6, 5, 0 },
244 { "fixup_Mips_64", 0, 64, 0 },
245 { "fixup_Mips_TLSGD", 0, 16, 0 },
246 { "fixup_Mips_GOTTPREL", 0, 16, 0 },
247 { "fixup_Mips_TPREL_HI", 0, 16, 0 },
248 { "fixup_Mips_TPREL_LO", 0, 16, 0 },
249 { "fixup_Mips_TLSLDM", 0, 16, 0 },
250 { "fixup_Mips_DTPREL_HI", 0, 16, 0 },
251 { "fixup_Mips_DTPREL_LO", 0, 16, 0 },
252 { "fixup_Mips_Branch_PCRel", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
253 { "fixup_Mips_GPOFF_HI", 0, 16, 0 },
254 { "fixup_Mips_GPOFF_LO", 0, 16, 0 },
255 { "fixup_Mips_GOT_PAGE", 0, 16, 0 },
256 { "fixup_Mips_GOT_OFST", 0, 16, 0 },
257 { "fixup_Mips_GOT_DISP", 0, 16, 0 },
258 { "fixup_Mips_HIGHER", 0, 16, 0 },
259 { "fixup_Mips_HIGHEST", 0, 16, 0 },
260 { "fixup_Mips_GOT_HI16", 0, 16, 0 },
261 { "fixup_Mips_GOT_LO16", 0, 16, 0 },
262 { "fixup_Mips_CALL_HI16", 0, 16, 0 },
263 { "fixup_Mips_CALL_LO16", 0, 16, 0 },
264 { "fixup_Mips_PC18_S3", 0, 18, MCFixupKindInfo::FKF_IsPCRel },
265 { "fixup_MIPS_PC19_S2", 0, 19, MCFixupKindInfo::FKF_IsPCRel },
266 { "fixup_MIPS_PC21_S2", 0, 21, MCFixupKindInfo::FKF_IsPCRel },
267 { "fixup_MIPS_PC26_S2", 0, 26, MCFixupKindInfo::FKF_IsPCRel },
268 { "fixup_MIPS_PCHI16", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
269 { "fixup_MIPS_PCLO16", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
270 { "fixup_MICROMIPS_26_S1", 0, 26, 0 },
271 { "fixup_MICROMIPS_HI16", 0, 16, 0 },
272 { "fixup_MICROMIPS_LO16", 0, 16, 0 },
273 { "fixup_MICROMIPS_GOT16", 0, 16, 0 },
274 { "fixup_MICROMIPS_PC16_S1", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
275 { "fixup_MICROMIPS_CALL16", 0, 16, 0 },
276 { "fixup_MICROMIPS_GOT_DISP", 0, 16, 0 },
277 { "fixup_MICROMIPS_GOT_PAGE", 0, 16, 0 },
278 { "fixup_MICROMIPS_GOT_OFST", 0, 16, 0 },
279 { "fixup_MICROMIPS_TLS_GD", 0, 16, 0 },
280 { "fixup_MICROMIPS_TLS_LDM", 0, 16, 0 },
281 { "fixup_MICROMIPS_TLS_DTPREL_HI16", 0, 16, 0 },
282 { "fixup_MICROMIPS_TLS_DTPREL_LO16", 0, 16, 0 },
283 { "fixup_MICROMIPS_TLS_TPREL_HI16", 0, 16, 0 },
284 { "fixup_MICROMIPS_TLS_TPREL_LO16", 0, 16, 0 }
285 };
286
287 const static MCFixupKindInfo BigEndianInfos[Mips::NumTargetFixupKinds] = {
288 // This table *must* be in same the order of fixup_* kinds in
289 // MipsFixupKinds.h.
290 //
291 // name offset bits flags
292 { "fixup_Mips_16", 16, 16, 0 },
293 { "fixup_Mips_32", 0, 32, 0 },
294 { "fixup_Mips_REL32", 0, 32, 0 },
295 { "fixup_Mips_26", 6, 26, 0 },
296 { "fixup_Mips_HI16", 16, 16, 0 },
297 { "fixup_Mips_LO16", 16, 16, 0 },
298 { "fixup_Mips_GPREL16", 16, 16, 0 },
299 { "fixup_Mips_LITERAL", 16, 16, 0 },
300 { "fixup_Mips_GOT_Global", 16, 16, 0 },
301 { "fixup_Mips_GOT_Local", 16, 16, 0 },
302 { "fixup_Mips_PC16", 16, 16, MCFixupKindInfo::FKF_IsPCRel },
303 { "fixup_Mips_CALL16", 16, 16, 0 },
304 { "fixup_Mips_GPREL32", 0, 32, 0 },
305 { "fixup_Mips_SHIFT5", 21, 5, 0 },
306 { "fixup_Mips_SHIFT6", 21, 5, 0 },
307 { "fixup_Mips_64", 0, 64, 0 },
308 { "fixup_Mips_TLSGD", 16, 16, 0 },
309 { "fixup_Mips_GOTTPREL", 16, 16, 0 },
310 { "fixup_Mips_TPREL_HI", 16, 16, 0 },
311 { "fixup_Mips_TPREL_LO", 16, 16, 0 },
312 { "fixup_Mips_TLSLDM", 16, 16, 0 },
313 { "fixup_Mips_DTPREL_HI", 16, 16, 0 },
314 { "fixup_Mips_DTPREL_LO", 16, 16, 0 },
315 { "fixup_Mips_Branch_PCRel",16, 16, MCFixupKindInfo::FKF_IsPCRel },
316 { "fixup_Mips_GPOFF_HI", 16, 16, 0 },
317 { "fixup_Mips_GPOFF_LO", 16, 16, 0 },
318 { "fixup_Mips_GOT_PAGE", 16, 16, 0 },
319 { "fixup_Mips_GOT_OFST", 16, 16, 0 },
320 { "fixup_Mips_GOT_DISP", 16, 16, 0 },
321 { "fixup_Mips_HIGHER", 16, 16, 0 },
322 { "fixup_Mips_HIGHEST", 16, 16, 0 },
323 { "fixup_Mips_GOT_HI16", 16, 16, 0 },
324 { "fixup_Mips_GOT_LO16", 16, 16, 0 },
325 { "fixup_Mips_CALL_HI16", 16, 16, 0 },
326 { "fixup_Mips_CALL_LO16", 16, 16, 0 },
327 { "fixup_Mips_PC18_S3", 14, 18, MCFixupKindInfo::FKF_IsPCRel },
328 { "fixup_MIPS_PC19_S2", 13, 19, MCFixupKindInfo::FKF_IsPCRel },
329 { "fixup_MIPS_PC21_S2", 11, 21, MCFixupKindInfo::FKF_IsPCRel },
330 { "fixup_MIPS_PC26_S2", 6, 26, MCFixupKindInfo::FKF_IsPCRel },
331 { "fixup_MIPS_PCHI16", 16, 16, MCFixupKindInfo::FKF_IsPCRel },
332 { "fixup_MIPS_PCLO16", 16, 16, MCFixupKindInfo::FKF_IsPCRel },
333 { "fixup_MICROMIPS_26_S1", 6, 26, 0 },
334 { "fixup_MICROMIPS_HI16", 16, 16, 0 },
335 { "fixup_MICROMIPS_LO16", 16, 16, 0 },
336 { "fixup_MICROMIPS_GOT16", 16, 16, 0 },
337 { "fixup_MICROMIPS_PC16_S1",16, 16, MCFixupKindInfo::FKF_IsPCRel },
338 { "fixup_MICROMIPS_CALL16", 16, 16, 0 },
339 { "fixup_MICROMIPS_GOT_DISP", 16, 16, 0 },
340 { "fixup_MICROMIPS_GOT_PAGE", 16, 16, 0 },
341 { "fixup_MICROMIPS_GOT_OFST", 16, 16, 0 },
342 { "fixup_MICROMIPS_TLS_GD", 16, 16, 0 },
343 { "fixup_MICROMIPS_TLS_LDM", 16, 16, 0 },
344 { "fixup_MICROMIPS_TLS_DTPREL_HI16", 16, 16, 0 },
345 { "fixup_MICROMIPS_TLS_DTPREL_LO16", 16, 16, 0 },
346 { "fixup_MICROMIPS_TLS_TPREL_HI16", 16, 16, 0 },
347 { "fixup_MICROMIPS_TLS_TPREL_LO16", 16, 16, 0 }
348 };
349
350 if (Kind < FirstTargetFixupKind)
351 return MCAsmBackend::getFixupKindInfo(Kind);
352
353 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
354 "Invalid kind!");
355
356 if (IsLittle)
357 return LittleEndianInfos[Kind - FirstTargetFixupKind];
358 return BigEndianInfos[Kind - FirstTargetFixupKind];
359 }
360
361 /// WriteNopData - Write an (optimal) nop sequence of Count bytes
362 /// to the given output. If the target cannot generate such a sequence,
363 /// it should return an error.
364 ///
365 /// \return - True on success.
writeNopData(uint64_t Count,MCObjectWriter * OW) const366 bool MipsAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
367 // Check for a less than instruction size number of bytes
368 // FIXME: 16 bit instructions are not handled yet here.
369 // We shouldn't be using a hard coded number for instruction size.
370 if (Count % 4) return false;
371
372 uint64_t NumNops = Count / 4;
373 for (uint64_t i = 0; i != NumNops; ++i)
374 OW->Write32(0);
375 return true;
376 }
377
378 /// processFixupValue - Target hook to process the literal value of a fixup
379 /// if necessary.
processFixupValue(const MCAssembler & Asm,const MCAsmLayout & Layout,const MCFixup & Fixup,const MCFragment * DF,const MCValue & Target,uint64_t & Value,bool & IsResolved)380 void MipsAsmBackend::processFixupValue(const MCAssembler &Asm,
381 const MCAsmLayout &Layout,
382 const MCFixup &Fixup,
383 const MCFragment *DF,
384 const MCValue &Target,
385 uint64_t &Value,
386 bool &IsResolved) {
387 // At this point we'll ignore the value returned by adjustFixupValue as
388 // we are only checking if the fixup can be applied correctly. We have
389 // access to MCContext from here which allows us to report a fatal error
390 // with *possibly* a source code location.
391 (void)adjustFixupValue(Fixup, Value, &Asm.getContext());
392 }
393
394 // MCAsmBackend
createMipsAsmBackendEL32(const Target & T,const MCRegisterInfo & MRI,StringRef TT,StringRef CPU)395 MCAsmBackend *llvm::createMipsAsmBackendEL32(const Target &T,
396 const MCRegisterInfo &MRI,
397 StringRef TT,
398 StringRef CPU) {
399 return new MipsAsmBackend(T, Triple(TT).getOS(),
400 /*IsLittle*/true, /*Is64Bit*/false);
401 }
402
createMipsAsmBackendEB32(const Target & T,const MCRegisterInfo & MRI,StringRef TT,StringRef CPU)403 MCAsmBackend *llvm::createMipsAsmBackendEB32(const Target &T,
404 const MCRegisterInfo &MRI,
405 StringRef TT,
406 StringRef CPU) {
407 return new MipsAsmBackend(T, Triple(TT).getOS(),
408 /*IsLittle*/false, /*Is64Bit*/false);
409 }
410
createMipsAsmBackendEL64(const Target & T,const MCRegisterInfo & MRI,StringRef TT,StringRef CPU)411 MCAsmBackend *llvm::createMipsAsmBackendEL64(const Target &T,
412 const MCRegisterInfo &MRI,
413 StringRef TT,
414 StringRef CPU) {
415 return new MipsAsmBackend(T, Triple(TT).getOS(),
416 /*IsLittle*/true, /*Is64Bit*/true);
417 }
418
createMipsAsmBackendEB64(const Target & T,const MCRegisterInfo & MRI,StringRef TT,StringRef CPU)419 MCAsmBackend *llvm::createMipsAsmBackendEB64(const Target &T,
420 const MCRegisterInfo &MRI,
421 StringRef TT,
422 StringRef CPU) {
423 return new MipsAsmBackend(T, Triple(TT).getOS(),
424 /*IsLittle*/false, /*Is64Bit*/true);
425 }
426