1 //===------ PPCDisassembler.cpp - Disassembler for PowerPC ------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9
10 #include "PPC.h"
11 #include "llvm/MC/MCDisassembler.h"
12 #include "llvm/MC/MCFixedLenDisassembler.h"
13 #include "llvm/MC/MCInst.h"
14 #include "llvm/MC/MCSubtargetInfo.h"
15 #include "llvm/Support/MemoryObject.h"
16 #include "llvm/Support/TargetRegistry.h"
17
18 using namespace llvm;
19
20 #define DEBUG_TYPE "ppc-disassembler"
21
22 typedef MCDisassembler::DecodeStatus DecodeStatus;
23
24 namespace {
25 class PPCDisassembler : public MCDisassembler {
26 public:
PPCDisassembler(const MCSubtargetInfo & STI,MCContext & Ctx)27 PPCDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx)
28 : MCDisassembler(STI, Ctx) {}
~PPCDisassembler()29 virtual ~PPCDisassembler() {}
30
31 // Override MCDisassembler.
32 virtual DecodeStatus getInstruction(MCInst &instr,
33 uint64_t &size,
34 const MemoryObject ®ion,
35 uint64_t address,
36 raw_ostream &vStream,
37 raw_ostream &cStream) const override;
38 };
39 } // end anonymous namespace
40
createPPCDisassembler(const Target & T,const MCSubtargetInfo & STI,MCContext & Ctx)41 static MCDisassembler *createPPCDisassembler(const Target &T,
42 const MCSubtargetInfo &STI,
43 MCContext &Ctx) {
44 return new PPCDisassembler(STI, Ctx);
45 }
46
LLVMInitializePowerPCDisassembler()47 extern "C" void LLVMInitializePowerPCDisassembler() {
48 // Register the disassembler for each target.
49 TargetRegistry::RegisterMCDisassembler(ThePPC32Target,
50 createPPCDisassembler);
51 TargetRegistry::RegisterMCDisassembler(ThePPC64Target,
52 createPPCDisassembler);
53 TargetRegistry::RegisterMCDisassembler(ThePPC64LETarget,
54 createPPCDisassembler);
55 }
56
57 // FIXME: These can be generated by TableGen from the existing register
58 // encoding values!
59
60 static const unsigned CRRegs[] = {
61 PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3,
62 PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7
63 };
64
65 static const unsigned CRBITRegs[] = {
66 PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN,
67 PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN,
68 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
69 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
70 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
71 PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN,
72 PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN,
73 PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN
74 };
75
76 static const unsigned FRegs[] = {
77 PPC::F0, PPC::F1, PPC::F2, PPC::F3,
78 PPC::F4, PPC::F5, PPC::F6, PPC::F7,
79 PPC::F8, PPC::F9, PPC::F10, PPC::F11,
80 PPC::F12, PPC::F13, PPC::F14, PPC::F15,
81 PPC::F16, PPC::F17, PPC::F18, PPC::F19,
82 PPC::F20, PPC::F21, PPC::F22, PPC::F23,
83 PPC::F24, PPC::F25, PPC::F26, PPC::F27,
84 PPC::F28, PPC::F29, PPC::F30, PPC::F31
85 };
86
87 static const unsigned VRegs[] = {
88 PPC::V0, PPC::V1, PPC::V2, PPC::V3,
89 PPC::V4, PPC::V5, PPC::V6, PPC::V7,
90 PPC::V8, PPC::V9, PPC::V10, PPC::V11,
91 PPC::V12, PPC::V13, PPC::V14, PPC::V15,
92 PPC::V16, PPC::V17, PPC::V18, PPC::V19,
93 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
94 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
95 PPC::V28, PPC::V29, PPC::V30, PPC::V31
96 };
97
98 static const unsigned VSRegs[] = {
99 PPC::VSL0, PPC::VSL1, PPC::VSL2, PPC::VSL3,
100 PPC::VSL4, PPC::VSL5, PPC::VSL6, PPC::VSL7,
101 PPC::VSL8, PPC::VSL9, PPC::VSL10, PPC::VSL11,
102 PPC::VSL12, PPC::VSL13, PPC::VSL14, PPC::VSL15,
103 PPC::VSL16, PPC::VSL17, PPC::VSL18, PPC::VSL19,
104 PPC::VSL20, PPC::VSL21, PPC::VSL22, PPC::VSL23,
105 PPC::VSL24, PPC::VSL25, PPC::VSL26, PPC::VSL27,
106 PPC::VSL28, PPC::VSL29, PPC::VSL30, PPC::VSL31,
107
108 PPC::VSH0, PPC::VSH1, PPC::VSH2, PPC::VSH3,
109 PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7,
110 PPC::VSH8, PPC::VSH9, PPC::VSH10, PPC::VSH11,
111 PPC::VSH12, PPC::VSH13, PPC::VSH14, PPC::VSH15,
112 PPC::VSH16, PPC::VSH17, PPC::VSH18, PPC::VSH19,
113 PPC::VSH20, PPC::VSH21, PPC::VSH22, PPC::VSH23,
114 PPC::VSH24, PPC::VSH25, PPC::VSH26, PPC::VSH27,
115 PPC::VSH28, PPC::VSH29, PPC::VSH30, PPC::VSH31
116 };
117
118 static const unsigned VSFRegs[] = {
119 PPC::F0, PPC::F1, PPC::F2, PPC::F3,
120 PPC::F4, PPC::F5, PPC::F6, PPC::F7,
121 PPC::F8, PPC::F9, PPC::F10, PPC::F11,
122 PPC::F12, PPC::F13, PPC::F14, PPC::F15,
123 PPC::F16, PPC::F17, PPC::F18, PPC::F19,
124 PPC::F20, PPC::F21, PPC::F22, PPC::F23,
125 PPC::F24, PPC::F25, PPC::F26, PPC::F27,
126 PPC::F28, PPC::F29, PPC::F30, PPC::F31,
127
128 PPC::VF0, PPC::VF1, PPC::VF2, PPC::VF3,
129 PPC::VF4, PPC::VF5, PPC::VF6, PPC::VF7,
130 PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11,
131 PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15,
132 PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19,
133 PPC::VF20, PPC::VF21, PPC::VF22, PPC::VF23,
134 PPC::VF24, PPC::VF25, PPC::VF26, PPC::VF27,
135 PPC::VF28, PPC::VF29, PPC::VF30, PPC::VF31
136 };
137
138 static const unsigned GPRegs[] = {
139 PPC::R0, PPC::R1, PPC::R2, PPC::R3,
140 PPC::R4, PPC::R5, PPC::R6, PPC::R7,
141 PPC::R8, PPC::R9, PPC::R10, PPC::R11,
142 PPC::R12, PPC::R13, PPC::R14, PPC::R15,
143 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
144 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
145 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
146 PPC::R28, PPC::R29, PPC::R30, PPC::R31
147 };
148
149 static const unsigned GP0Regs[] = {
150 PPC::ZERO, PPC::R1, PPC::R2, PPC::R3,
151 PPC::R4, PPC::R5, PPC::R6, PPC::R7,
152 PPC::R8, PPC::R9, PPC::R10, PPC::R11,
153 PPC::R12, PPC::R13, PPC::R14, PPC::R15,
154 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
155 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
156 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
157 PPC::R28, PPC::R29, PPC::R30, PPC::R31
158 };
159
160 static const unsigned G8Regs[] = {
161 PPC::X0, PPC::X1, PPC::X2, PPC::X3,
162 PPC::X4, PPC::X5, PPC::X6, PPC::X7,
163 PPC::X8, PPC::X9, PPC::X10, PPC::X11,
164 PPC::X12, PPC::X13, PPC::X14, PPC::X15,
165 PPC::X16, PPC::X17, PPC::X18, PPC::X19,
166 PPC::X20, PPC::X21, PPC::X22, PPC::X23,
167 PPC::X24, PPC::X25, PPC::X26, PPC::X27,
168 PPC::X28, PPC::X29, PPC::X30, PPC::X31
169 };
170
171 template <std::size_t N>
decodeRegisterClass(MCInst & Inst,uint64_t RegNo,const unsigned (& Regs)[N])172 static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo,
173 const unsigned (&Regs)[N]) {
174 assert(RegNo < N && "Invalid register number");
175 Inst.addOperand(MCOperand::CreateReg(Regs[RegNo]));
176 return MCDisassembler::Success;
177 }
178
DecodeCRRCRegisterClass(MCInst & Inst,uint64_t RegNo,uint64_t Address,const void * Decoder)179 static DecodeStatus DecodeCRRCRegisterClass(MCInst &Inst, uint64_t RegNo,
180 uint64_t Address,
181 const void *Decoder) {
182 return decodeRegisterClass(Inst, RegNo, CRRegs);
183 }
184
DecodeCRBITRCRegisterClass(MCInst & Inst,uint64_t RegNo,uint64_t Address,const void * Decoder)185 static DecodeStatus DecodeCRBITRCRegisterClass(MCInst &Inst, uint64_t RegNo,
186 uint64_t Address,
187 const void *Decoder) {
188 return decodeRegisterClass(Inst, RegNo, CRBITRegs);
189 }
190
DecodeF4RCRegisterClass(MCInst & Inst,uint64_t RegNo,uint64_t Address,const void * Decoder)191 static DecodeStatus DecodeF4RCRegisterClass(MCInst &Inst, uint64_t RegNo,
192 uint64_t Address,
193 const void *Decoder) {
194 return decodeRegisterClass(Inst, RegNo, FRegs);
195 }
196
DecodeF8RCRegisterClass(MCInst & Inst,uint64_t RegNo,uint64_t Address,const void * Decoder)197 static DecodeStatus DecodeF8RCRegisterClass(MCInst &Inst, uint64_t RegNo,
198 uint64_t Address,
199 const void *Decoder) {
200 return decodeRegisterClass(Inst, RegNo, FRegs);
201 }
202
DecodeVRRCRegisterClass(MCInst & Inst,uint64_t RegNo,uint64_t Address,const void * Decoder)203 static DecodeStatus DecodeVRRCRegisterClass(MCInst &Inst, uint64_t RegNo,
204 uint64_t Address,
205 const void *Decoder) {
206 return decodeRegisterClass(Inst, RegNo, VRegs);
207 }
208
DecodeVSRCRegisterClass(MCInst & Inst,uint64_t RegNo,uint64_t Address,const void * Decoder)209 static DecodeStatus DecodeVSRCRegisterClass(MCInst &Inst, uint64_t RegNo,
210 uint64_t Address,
211 const void *Decoder) {
212 return decodeRegisterClass(Inst, RegNo, VSRegs);
213 }
214
DecodeVSFRCRegisterClass(MCInst & Inst,uint64_t RegNo,uint64_t Address,const void * Decoder)215 static DecodeStatus DecodeVSFRCRegisterClass(MCInst &Inst, uint64_t RegNo,
216 uint64_t Address,
217 const void *Decoder) {
218 return decodeRegisterClass(Inst, RegNo, VSFRegs);
219 }
220
DecodeGPRCRegisterClass(MCInst & Inst,uint64_t RegNo,uint64_t Address,const void * Decoder)221 static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint64_t RegNo,
222 uint64_t Address,
223 const void *Decoder) {
224 return decodeRegisterClass(Inst, RegNo, GPRegs);
225 }
226
DecodeGPRC_NOR0RegisterClass(MCInst & Inst,uint64_t RegNo,uint64_t Address,const void * Decoder)227 static DecodeStatus DecodeGPRC_NOR0RegisterClass(MCInst &Inst, uint64_t RegNo,
228 uint64_t Address,
229 const void *Decoder) {
230 return decodeRegisterClass(Inst, RegNo, GP0Regs);
231 }
232
DecodeG8RCRegisterClass(MCInst & Inst,uint64_t RegNo,uint64_t Address,const void * Decoder)233 static DecodeStatus DecodeG8RCRegisterClass(MCInst &Inst, uint64_t RegNo,
234 uint64_t Address,
235 const void *Decoder) {
236 return decodeRegisterClass(Inst, RegNo, G8Regs);
237 }
238
239 #define DecodePointerLikeRegClass0 DecodeGPRCRegisterClass
240 #define DecodePointerLikeRegClass1 DecodeGPRC_NOR0RegisterClass
241
242 template<unsigned N>
decodeUImmOperand(MCInst & Inst,uint64_t Imm,int64_t Address,const void * Decoder)243 static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm,
244 int64_t Address, const void *Decoder) {
245 assert(isUInt<N>(Imm) && "Invalid immediate");
246 Inst.addOperand(MCOperand::CreateImm(Imm));
247 return MCDisassembler::Success;
248 }
249
250 template<unsigned N>
decodeSImmOperand(MCInst & Inst,uint64_t Imm,int64_t Address,const void * Decoder)251 static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm,
252 int64_t Address, const void *Decoder) {
253 assert(isUInt<N>(Imm) && "Invalid immediate");
254 Inst.addOperand(MCOperand::CreateImm(SignExtend64<N>(Imm)));
255 return MCDisassembler::Success;
256 }
257
decodeMemRIOperands(MCInst & Inst,uint64_t Imm,int64_t Address,const void * Decoder)258 static DecodeStatus decodeMemRIOperands(MCInst &Inst, uint64_t Imm,
259 int64_t Address, const void *Decoder) {
260 // Decode the memri field (imm, reg), which has the low 16-bits as the
261 // displacement and the next 5 bits as the register #.
262
263 uint64_t Base = Imm >> 16;
264 uint64_t Disp = Imm & 0xFFFF;
265
266 assert(Base < 32 && "Invalid base register");
267
268 switch (Inst.getOpcode()) {
269 default: break;
270 case PPC::LBZU:
271 case PPC::LHAU:
272 case PPC::LHZU:
273 case PPC::LWZU:
274 case PPC::LFSU:
275 case PPC::LFDU:
276 // Add the tied output operand.
277 Inst.addOperand(MCOperand::CreateReg(GP0Regs[Base]));
278 break;
279 case PPC::STBU:
280 case PPC::STHU:
281 case PPC::STWU:
282 case PPC::STFSU:
283 case PPC::STFDU:
284 Inst.insert(Inst.begin(), MCOperand::CreateReg(GP0Regs[Base]));
285 break;
286 }
287
288 Inst.addOperand(MCOperand::CreateImm(SignExtend64<16>(Disp)));
289 Inst.addOperand(MCOperand::CreateReg(GP0Regs[Base]));
290 return MCDisassembler::Success;
291 }
292
decodeMemRIXOperands(MCInst & Inst,uint64_t Imm,int64_t Address,const void * Decoder)293 static DecodeStatus decodeMemRIXOperands(MCInst &Inst, uint64_t Imm,
294 int64_t Address, const void *Decoder) {
295 // Decode the memrix field (imm, reg), which has the low 14-bits as the
296 // displacement and the next 5 bits as the register #.
297
298 uint64_t Base = Imm >> 14;
299 uint64_t Disp = Imm & 0x3FFF;
300
301 assert(Base < 32 && "Invalid base register");
302
303 if (Inst.getOpcode() == PPC::LDU)
304 // Add the tied output operand.
305 Inst.addOperand(MCOperand::CreateReg(GP0Regs[Base]));
306 else if (Inst.getOpcode() == PPC::STDU)
307 Inst.insert(Inst.begin(), MCOperand::CreateReg(GP0Regs[Base]));
308
309 Inst.addOperand(MCOperand::CreateImm(SignExtend64<16>(Disp << 2)));
310 Inst.addOperand(MCOperand::CreateReg(GP0Regs[Base]));
311 return MCDisassembler::Success;
312 }
313
decodeCRBitMOperand(MCInst & Inst,uint64_t Imm,int64_t Address,const void * Decoder)314 static DecodeStatus decodeCRBitMOperand(MCInst &Inst, uint64_t Imm,
315 int64_t Address, const void *Decoder) {
316 // The cr bit encoding is 0x80 >> cr_reg_num.
317
318 unsigned Zeros = countTrailingZeros(Imm);
319 assert(Zeros < 8 && "Invalid CR bit value");
320
321 Inst.addOperand(MCOperand::CreateReg(CRRegs[7 - Zeros]));
322 return MCDisassembler::Success;
323 }
324
325 #include "PPCGenDisassemblerTables.inc"
326
getInstruction(MCInst & MI,uint64_t & Size,const MemoryObject & Region,uint64_t Address,raw_ostream & os,raw_ostream & cs) const327 DecodeStatus PPCDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
328 const MemoryObject &Region,
329 uint64_t Address,
330 raw_ostream &os,
331 raw_ostream &cs) const {
332 // Get the four bytes of the instruction.
333 uint8_t Bytes[4];
334 Size = 4;
335 if (Region.readBytes(Address, Size, Bytes) == -1) {
336 Size = 0;
337 return MCDisassembler::Fail;
338 }
339
340 // The instruction is big-endian encoded.
341 uint32_t Inst = (Bytes[0] << 24) |
342 (Bytes[1] << 16) |
343 (Bytes[2] << 8) |
344 (Bytes[3] << 0);
345
346 return decodeInstruction(DecoderTable32, MI, Inst, Address, this, STI);
347 }
348
349