1; RUN: llc < %s -O0 -fast-isel-abort -mtriple=arm64-apple-darwin -mcpu=cyclone | FileCheck %s 2 3define void @branch1() nounwind uwtable ssp { 4 %x = alloca i32, align 4 5 store i32 0, i32* %x, align 4 6 %1 = load i32* %x, align 4 7 %2 = icmp ne i32 %1, 0 8 br i1 %2, label %3, label %4 9 10; <label>:3 ; preds = %0 11 br label %4 12 13; <label>:4 ; preds = %3, %0 14 ret void 15} 16 17define void @branch2() nounwind uwtable ssp { 18 %1 = alloca i32, align 4 19 %x = alloca i32, align 4 20 %y = alloca i32, align 4 21 %z = alloca i32, align 4 22 store i32 0, i32* %1 23 store i32 1, i32* %y, align 4 24 store i32 1, i32* %x, align 4 25 store i32 0, i32* %z, align 4 26 %2 = load i32* %x, align 4 27 %3 = icmp ne i32 %2, 0 28 br i1 %3, label %4, label %5 29 30; <label>:4 ; preds = %0 31 store i32 0, i32* %1 32 br label %14 33 34; <label>:5 ; preds = %0 35 %6 = load i32* %y, align 4 36 %7 = icmp ne i32 %6, 0 37 br i1 %7, label %8, label %13 38 39; <label>:8 ; preds = %5 40 %9 = load i32* %z, align 4 41 %10 = icmp ne i32 %9, 0 42 br i1 %10, label %11, label %12 43 44; <label>:11 ; preds = %8 45 store i32 1, i32* %1 46 br label %14 47 48; <label>:12 ; preds = %8 49 store i32 0, i32* %1 50 br label %14 51 52; <label>:13 ; preds = %5 53 br label %14 54 55; <label>:14 ; preds = %4, %11, %12, %13 56 %15 = load i32* %1 57 ret void 58} 59 60define void @true_() nounwind uwtable ssp { 61; CHECK: @true_ 62; CHECK: b LBB2_1 63 br i1 true, label %1, label %2 64 65; <label>:1 66; CHECK: LBB2_1 67 br label %2 68 69; <label>:2 70 ret void 71} 72 73define void @false_() nounwind uwtable ssp { 74; CHECK: @false_ 75; CHECK: b LBB3_2 76 br i1 false, label %1, label %2 77 78; <label>:1 79 br label %2 80 81; <label>:2 82; CHECK: LBB3_2 83 ret void 84} 85 86define zeroext i8 @trunc_(i8 zeroext %a, i16 zeroext %b, i32 %c, i64 %d) { 87entry: 88 %a.addr = alloca i8, align 1 89 %b.addr = alloca i16, align 2 90 %c.addr = alloca i32, align 4 91 %d.addr = alloca i64, align 8 92 store i8 %a, i8* %a.addr, align 1 93 store i16 %b, i16* %b.addr, align 2 94 store i32 %c, i32* %c.addr, align 4 95 store i64 %d, i64* %d.addr, align 8 96 %0 = load i16* %b.addr, align 2 97; CHECK: and w0, w0, #0x1 98; CHECK: subs w0, w0, #0 99; CHECK: b.eq LBB4_2 100 %conv = trunc i16 %0 to i1 101 br i1 %conv, label %if.then, label %if.end 102 103if.then: ; preds = %entry 104 call void @foo1() 105 br label %if.end 106 107if.end: ; preds = %if.then, %entry 108 %1 = load i32* %c.addr, align 4 109; CHECK: and w[[REG:[0-9]+]], w{{[0-9]+}}, #0x1 110; CHECK: subs w{{[0-9]+}}, w[[REG]], #0 111; CHECK: b.eq LBB4_4 112 %conv1 = trunc i32 %1 to i1 113 br i1 %conv1, label %if.then3, label %if.end4 114 115if.then3: ; preds = %if.end 116 call void @foo1() 117 br label %if.end4 118 119if.end4: ; preds = %if.then3, %if.end 120 %2 = load i64* %d.addr, align 8 121; CHECK: subs w{{[0-9]+}}, w{{[0-9]+}}, #0 122; CHECK: b.eq LBB4_6 123 %conv5 = trunc i64 %2 to i1 124 br i1 %conv5, label %if.then7, label %if.end8 125 126if.then7: ; preds = %if.end4 127 call void @foo1() 128 br label %if.end8 129 130if.end8: ; preds = %if.then7, %if.end4 131 %3 = load i8* %a.addr, align 1 132 ret i8 %3 133} 134 135declare void @foo1() 136 137; rdar://15174028 138define i32 @trunc64(i64 %foo) nounwind { 139; CHECK: trunc64 140; CHECK: orr [[REG:x[0-9]+]], xzr, #0x1 141; CHECK: and [[REG2:x[0-9]+]], x0, [[REG]] 142; CHECK: mov x[[REG3:[0-9]+]], [[REG2]] 143; CHECK: and [[REG4:w[0-9]+]], w[[REG3]], #0x1 144; CHECK: subs {{w[0-9]+}}, [[REG4]], #0 145; CHECK: b.eq LBB5_2 146 %a = and i64 %foo, 1 147 %b = trunc i64 %a to i1 148 br i1 %b, label %if.then, label %if.else 149 150if.then: 151 ret i32 1 152 153if.else: 154 ret i32 0 155} 156