1; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple -no-integrated-as | FileCheck %s 2 3; rdar://9167275 4 5define i32 @t1() nounwind ssp { 6entry: 7; CHECK-LABEL: t1: 8; CHECK: mov {{w[0-9]+}}, 7 9 %0 = tail call i32 asm "mov ${0:w}, 7", "=r"() nounwind 10 ret i32 %0 11} 12 13define i64 @t2() nounwind ssp { 14entry: 15; CHECK-LABEL: t2: 16; CHECK: mov {{x[0-9]+}}, 7 17 %0 = tail call i64 asm "mov $0, 7", "=r"() nounwind 18 ret i64 %0 19} 20 21define i64 @t3() nounwind ssp { 22entry: 23; CHECK-LABEL: t3: 24; CHECK: mov {{w[0-9]+}}, 7 25 %0 = tail call i64 asm "mov ${0:w}, 7", "=r"() nounwind 26 ret i64 %0 27} 28 29; rdar://9281206 30 31define void @t4(i64 %op) nounwind { 32entry: 33; CHECK-LABEL: t4: 34; CHECK: mov x0, {{x[0-9]+}}; svc #0 35 %0 = tail call i64 asm sideeffect "mov x0, $1; svc #0;", "=r,r,r,~{x0}"(i64 %op, i64 undef) nounwind 36 ret void 37} 38 39; rdar://9394290 40 41define float @t5(float %x) nounwind { 42entry: 43; CHECK-LABEL: t5: 44; CHECK: fadd {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}} 45 %0 = tail call float asm "fadd ${0:s}, ${0:s}, ${0:s}", "=w,0"(float %x) nounwind 46 ret float %0 47} 48 49; rdar://9553599 50 51define zeroext i8 @t6(i8* %src) nounwind { 52entry: 53; CHECK-LABEL: t6: 54; CHECK: ldtrb {{w[0-9]+}}, [{{x[0-9]+}}] 55 %0 = tail call i8 asm "ldtrb ${0:w}, [$1]", "=r,r"(i8* %src) nounwind 56 ret i8 %0 57} 58 59define void @t7(i8* %f, i32 %g) nounwind { 60entry: 61 %f.addr = alloca i8*, align 8 62 store i8* %f, i8** %f.addr, align 8 63 ; CHECK-LABEL: t7: 64 ; CHECK: str {{w[0-9]+}}, [{{x[0-9]+}}] 65 call void asm "str ${1:w}, $0", "=*Q,r"(i8** %f.addr, i32 %g) nounwind 66 ret void 67} 68 69; rdar://10258229 70; ARM64TargetLowering::getRegForInlineAsmConstraint() should recognize 'v' 71; registers. 72define void @t8() nounwind ssp { 73entry: 74; CHECK-LABEL: t8: 75; CHECK: stp {{d[0-9]+}}, {{d[0-9]+}}, [sp, #-16] 76 tail call void asm sideeffect "nop", "~{v8}"() nounwind 77 ret void 78} 79 80define i32 @constraint_I(i32 %i, i32 %j) nounwind { 81entry: 82 ; CHECK-LABEL: constraint_I: 83 %0 = tail call i32 asm sideeffect "add ${0:w}, ${1:w}, $2", "=r,r,I"(i32 %i, i32 16773120) nounwind 84 ; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, #16773120 85 %1 = tail call i32 asm sideeffect "add ${0:w}, ${1:w}, $2", "=r,r,I"(i32 %i, i32 4096) nounwind 86 ; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, #4096 87 ret i32 %1 88} 89 90define i32 @constraint_J(i32 %i, i32 %j) nounwind { 91entry: 92 ; CHECK-LABEL: constraint_J: 93 %0 = tail call i32 asm sideeffect "sub ${0:w}, ${1:w}, $2", "=r,r,J"(i32 %i, i32 -16773120) nounwind 94 ; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, #4278194176 95 %1 = tail call i32 asm sideeffect "sub ${0:w}, ${1:w}, $2", "=r,r,J"(i32 %i, i32 -1) nounwind 96 ; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, #4294967295 97 ret i32 %1 98} 99 100define i32 @constraint_KL(i32 %i, i32 %j) nounwind { 101entry: 102 ; CHECK-LABEL: constraint_KL: 103 %0 = tail call i32 asm sideeffect "eor ${0:w}, ${1:w}, $2", "=r,r,K"(i32 %i, i32 255) nounwind 104 ; CHECK: eor {{w[0-9]+}}, {{w[0-9]+}}, #255 105 %1 = tail call i32 asm sideeffect "eor ${0:w}, ${1:w}, $2", "=r,r,L"(i32 %i, i64 16711680) nounwind 106 ; CHECK: eor {{w[0-9]+}}, {{w[0-9]+}}, #16711680 107 ret i32 %1 108} 109 110define i32 @constraint_MN(i32 %i, i32 %j) nounwind { 111entry: 112 ; CHECK-LABEL: constraint_MN: 113 %0 = tail call i32 asm sideeffect "movk ${0:w}, $1", "=r,M"(i32 65535) nounwind 114 ; CHECK: movk {{w[0-9]+}}, #65535 115 %1 = tail call i32 asm sideeffect "movz ${0:w}, $1", "=r,N"(i64 0) nounwind 116 ; CHECK: movz {{w[0-9]+}}, #0 117 ret i32 %1 118} 119 120define void @t9() nounwind { 121entry: 122 ; CHECK-LABEL: t9: 123 %data = alloca <2 x double>, align 16 124 %0 = load <2 x double>* %data, align 16 125 call void asm sideeffect "mov.2d v4, $0\0A", "w,~{v4}"(<2 x double> %0) nounwind 126 ; CHECK: mov.2d v4, {{v[0-9]+}} 127 ret void 128} 129 130define void @t10() nounwind { 131entry: 132 ; CHECK-LABEL: t10: 133 %data = alloca <2 x float>, align 8 134 %a = alloca [2 x float], align 4 135 %arraydecay = getelementptr inbounds [2 x float]* %a, i32 0, i32 0 136 %0 = load <2 x float>* %data, align 8 137 call void asm sideeffect "ldr ${1:q}, [$0]\0A", "r,w"(float* %arraydecay, <2 x float> %0) nounwind 138 ; CHECK: ldr {{q[0-9]+}}, [{{x[0-9]+}}] 139 call void asm sideeffect "ldr ${1:d}, [$0]\0A", "r,w"(float* %arraydecay, <2 x float> %0) nounwind 140 ; CHECK: ldr {{d[0-9]+}}, [{{x[0-9]+}}] 141 call void asm sideeffect "ldr ${1:s}, [$0]\0A", "r,w"(float* %arraydecay, <2 x float> %0) nounwind 142 ; CHECK: ldr {{s[0-9]+}}, [{{x[0-9]+}}] 143 call void asm sideeffect "ldr ${1:h}, [$0]\0A", "r,w"(float* %arraydecay, <2 x float> %0) nounwind 144 ; CHECK: ldr {{h[0-9]+}}, [{{x[0-9]+}}] 145 call void asm sideeffect "ldr ${1:b}, [$0]\0A", "r,w"(float* %arraydecay, <2 x float> %0) nounwind 146 ; CHECK: ldr {{b[0-9]+}}, [{{x[0-9]+}}] 147 ret void 148} 149 150define void @t11() nounwind { 151entry: 152 ; CHECK-LABEL: t11: 153 %a = alloca i32, align 4 154 %0 = load i32* %a, align 4 155 call void asm sideeffect "mov ${1:x}, ${0:x}\0A", "r,i"(i32 %0, i32 0) nounwind 156 ; CHECK: mov xzr, {{x[0-9]+}} 157 %1 = load i32* %a, align 4 158 call void asm sideeffect "mov ${1:w}, ${0:w}\0A", "r,i"(i32 %1, i32 0) nounwind 159 ; CHECK: mov wzr, {{w[0-9]+}} 160 ret void 161} 162 163define void @t12() nounwind { 164entry: 165 ; CHECK-LABEL: t12: 166 %data = alloca <4 x float>, align 16 167 %0 = load <4 x float>* %data, align 16 168 call void asm sideeffect "mov.2d v4, $0\0A", "x,~{v4}"(<4 x float> %0) nounwind 169 ; CHECK mov.2d v4, {{v([0-9])|(1[0-5])}} 170 ret void 171} 172 173define void @t13() nounwind { 174entry: 175 ; CHECK-LABEL: t13: 176 tail call void asm sideeffect "mov x4, $0\0A", "N"(i64 1311673391471656960) nounwind 177 ; CHECK: mov x4, #1311673391471656960 178 tail call void asm sideeffect "mov x4, $0\0A", "N"(i64 -4662) nounwind 179 ; CHECK: mov x4, #-4662 180 tail call void asm sideeffect "mov x4, $0\0A", "N"(i64 4660) nounwind 181 ; CHECK: mov x4, #4660 182 call void asm sideeffect "mov x4, $0\0A", "N"(i64 -71777214294589696) nounwind 183 ; CHECK: mov x4, #-71777214294589696 184 ret void 185} 186 187define void @t14() nounwind { 188entry: 189 ; CHECK-LABEL: t14: 190 tail call void asm sideeffect "mov w4, $0\0A", "M"(i32 305397760) nounwind 191 ; CHECK: mov w4, #305397760 192 tail call void asm sideeffect "mov w4, $0\0A", "M"(i32 -4662) nounwind 193 ; CHECK: mov w4, #4294962634 194 tail call void asm sideeffect "mov w4, $0\0A", "M"(i32 4660) nounwind 195 ; CHECK: mov w4, #4660 196 call void asm sideeffect "mov w4, $0\0A", "M"(i32 -16711936) nounwind 197 ; CHECK: mov w4, #4278255360 198 ret void 199} 200 201define void @t15() nounwind { 202entry: 203 %0 = tail call double asm sideeffect "fmov $0, d8", "=r"() nounwind 204 ; CHECK: fmov {{x[0-9]+}}, d8 205 ret void 206} 207 208; rdar://problem/14285178 209 210define void @test_zero_reg(i32* %addr) { 211; CHECK-LABEL: test_zero_reg: 212 213 tail call void asm sideeffect "USE($0)", "z"(i32 0) nounwind 214; CHECK: USE(xzr) 215 216 tail call void asm sideeffect "USE(${0:w})", "zr"(i32 0) 217; CHECK: USE(wzr) 218 219 tail call void asm sideeffect "USE(${0:w})", "zr"(i32 1) 220; CHECK: orr [[VAL1:w[0-9]+]], wzr, #0x1 221; CHECK: USE([[VAL1]]) 222 223 tail call void asm sideeffect "USE($0), USE($1)", "z,z"(i32 0, i32 0) nounwind 224; CHECK: USE(xzr), USE(xzr) 225 226 tail call void asm sideeffect "USE($0), USE(${1:w})", "z,z"(i32 0, i32 0) nounwind 227; CHECK: USE(xzr), USE(wzr) 228 229 ret void 230} 231