1; Test the MSA floating-point conversion intrinsics that are encoded with the 2; 3RF instruction format. 3 4; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s 5; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s 6 7@llvm_mips_fexdo_h_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16 8@llvm_mips_fexdo_h_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16 9@llvm_mips_fexdo_h_RES = global <8 x half> <half 0.000000e+00, half 0.000000e+00, half 0.000000e+00, half 0.000000e+00, half 0.000000e+00, half 0.000000e+00, half 0.000000e+00, half 0.000000e+00>, align 16 10 11define void @llvm_mips_fexdo_h_test() nounwind { 12entry: 13 %0 = load <4 x float>* @llvm_mips_fexdo_h_ARG1 14 %1 = load <4 x float>* @llvm_mips_fexdo_h_ARG2 15 %2 = tail call <8 x half> @llvm.mips.fexdo.h(<4 x float> %0, <4 x float> %1) 16 store <8 x half> %2, <8 x half>* @llvm_mips_fexdo_h_RES 17 ret void 18} 19 20declare <8 x half> @llvm.mips.fexdo.h(<4 x float>, <4 x float>) nounwind 21 22; CHECK: llvm_mips_fexdo_h_test: 23; CHECK: ld.w 24; CHECK: ld.w 25; CHECK: fexdo.h 26; CHECK: st.h 27; CHECK: .size llvm_mips_fexdo_h_test 28; 29@llvm_mips_fexdo_w_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16 30@llvm_mips_fexdo_w_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16 31@llvm_mips_fexdo_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 16 32 33define void @llvm_mips_fexdo_w_test() nounwind { 34entry: 35 %0 = load <2 x double>* @llvm_mips_fexdo_w_ARG1 36 %1 = load <2 x double>* @llvm_mips_fexdo_w_ARG2 37 %2 = tail call <4 x float> @llvm.mips.fexdo.w(<2 x double> %0, <2 x double> %1) 38 store <4 x float> %2, <4 x float>* @llvm_mips_fexdo_w_RES 39 ret void 40} 41 42declare <4 x float> @llvm.mips.fexdo.w(<2 x double>, <2 x double>) nounwind 43 44; CHECK: llvm_mips_fexdo_w_test: 45; CHECK: ld.d 46; CHECK: ld.d 47; CHECK: fexdo.w 48; CHECK: st.w 49; CHECK: .size llvm_mips_fexdo_w_test 50; 51