1; RUN: llc -march=r600 -mcpu=SI < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s 2; RUN: llc -march=r600 -mcpu=cypress < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s 3 4declare float @llvm.ceil.f32(float) nounwind readnone 5declare <2 x float> @llvm.ceil.v2f32(<2 x float>) nounwind readnone 6declare <3 x float> @llvm.ceil.v3f32(<3 x float>) nounwind readnone 7declare <4 x float> @llvm.ceil.v4f32(<4 x float>) nounwind readnone 8declare <8 x float> @llvm.ceil.v8f32(<8 x float>) nounwind readnone 9declare <16 x float> @llvm.ceil.v16f32(<16 x float>) nounwind readnone 10 11; FUNC-LABEL: @fceil_f32: 12; SI: V_CEIL_F32_e32 13; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+\.[XYZW]]] 14; EG: CEIL {{\*? *}}[[RESULT]] 15define void @fceil_f32(float addrspace(1)* %out, float %x) { 16 %y = call float @llvm.ceil.f32(float %x) nounwind readnone 17 store float %y, float addrspace(1)* %out 18 ret void 19} 20 21; FUNC-LABEL: @fceil_v2f32: 22; SI: V_CEIL_F32_e32 23; SI: V_CEIL_F32_e32 24; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+]]{{\.[XYZW]}} 25; EG: CEIL {{\*? *}}[[RESULT]] 26; EG: CEIL {{\*? *}}[[RESULT]] 27define void @fceil_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %x) { 28 %y = call <2 x float> @llvm.ceil.v2f32(<2 x float> %x) nounwind readnone 29 store <2 x float> %y, <2 x float> addrspace(1)* %out 30 ret void 31} 32 33; FUNC-LABEL: @fceil_v3f32: 34; FIXME-SI: V_CEIL_F32_e32 35; FIXME-SI: V_CEIL_F32_e32 36; FIXME-SI: V_CEIL_F32_e32 37; FIXME-EG: v3 is treated as v2 and v1, hence 2 stores 38; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT1:T[0-9]+]]{{\.[XYZW]}} 39; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT2:T[0-9]+]]{{\.[XYZW]}} 40; EG-DAG: CEIL {{\*? *}}[[RESULT1]] 41; EG-DAG: CEIL {{\*? *}}[[RESULT2]] 42; EG-DAG: CEIL {{\*? *}}[[RESULT2]] 43define void @fceil_v3f32(<3 x float> addrspace(1)* %out, <3 x float> %x) { 44 %y = call <3 x float> @llvm.ceil.v3f32(<3 x float> %x) nounwind readnone 45 store <3 x float> %y, <3 x float> addrspace(1)* %out 46 ret void 47} 48 49; FUNC-LABEL: @fceil_v4f32: 50; SI: V_CEIL_F32_e32 51; SI: V_CEIL_F32_e32 52; SI: V_CEIL_F32_e32 53; SI: V_CEIL_F32_e32 54; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+]]{{\.[XYZW]}} 55; EG: CEIL {{\*? *}}[[RESULT]] 56; EG: CEIL {{\*? *}}[[RESULT]] 57; EG: CEIL {{\*? *}}[[RESULT]] 58; EG: CEIL {{\*? *}}[[RESULT]] 59define void @fceil_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %x) { 60 %y = call <4 x float> @llvm.ceil.v4f32(<4 x float> %x) nounwind readnone 61 store <4 x float> %y, <4 x float> addrspace(1)* %out 62 ret void 63} 64 65; FUNC-LABEL: @fceil_v8f32: 66; SI: V_CEIL_F32_e32 67; SI: V_CEIL_F32_e32 68; SI: V_CEIL_F32_e32 69; SI: V_CEIL_F32_e32 70; SI: V_CEIL_F32_e32 71; SI: V_CEIL_F32_e32 72; SI: V_CEIL_F32_e32 73; SI: V_CEIL_F32_e32 74; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT1:T[0-9]+]]{{\.[XYZW]}} 75; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT2:T[0-9]+]]{{\.[XYZW]}} 76; EG-DAG: CEIL {{\*? *}}[[RESULT1]] 77; EG-DAG: CEIL {{\*? *}}[[RESULT1]] 78; EG-DAG: CEIL {{\*? *}}[[RESULT1]] 79; EG-DAG: CEIL {{\*? *}}[[RESULT1]] 80; EG-DAG: CEIL {{\*? *}}[[RESULT2]] 81; EG-DAG: CEIL {{\*? *}}[[RESULT2]] 82; EG-DAG: CEIL {{\*? *}}[[RESULT2]] 83; EG-DAG: CEIL {{\*? *}}[[RESULT2]] 84define void @fceil_v8f32(<8 x float> addrspace(1)* %out, <8 x float> %x) { 85 %y = call <8 x float> @llvm.ceil.v8f32(<8 x float> %x) nounwind readnone 86 store <8 x float> %y, <8 x float> addrspace(1)* %out 87 ret void 88} 89 90; FUNC-LABEL: @fceil_v16f32: 91; SI: V_CEIL_F32_e32 92; SI: V_CEIL_F32_e32 93; SI: V_CEIL_F32_e32 94; SI: V_CEIL_F32_e32 95; SI: V_CEIL_F32_e32 96; SI: V_CEIL_F32_e32 97; SI: V_CEIL_F32_e32 98; SI: V_CEIL_F32_e32 99; SI: V_CEIL_F32_e32 100; SI: V_CEIL_F32_e32 101; SI: V_CEIL_F32_e32 102; SI: V_CEIL_F32_e32 103; SI: V_CEIL_F32_e32 104; SI: V_CEIL_F32_e32 105; SI: V_CEIL_F32_e32 106; SI: V_CEIL_F32_e32 107; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT1:T[0-9]+]]{{\.[XYZW]}} 108; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT2:T[0-9]+]]{{\.[XYZW]}} 109; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT3:T[0-9]+]]{{\.[XYZW]}} 110; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT4:T[0-9]+]]{{\.[XYZW]}} 111; EG-DAG: CEIL {{\*? *}}[[RESULT1]] 112; EG-DAG: CEIL {{\*? *}}[[RESULT1]] 113; EG-DAG: CEIL {{\*? *}}[[RESULT1]] 114; EG-DAG: CEIL {{\*? *}}[[RESULT1]] 115; EG-DAG: CEIL {{\*? *}}[[RESULT2]] 116; EG-DAG: CEIL {{\*? *}}[[RESULT2]] 117; EG-DAG: CEIL {{\*? *}}[[RESULT2]] 118; EG-DAG: CEIL {{\*? *}}[[RESULT2]] 119; EG-DAG: CEIL {{\*? *}}[[RESULT3]] 120; EG-DAG: CEIL {{\*? *}}[[RESULT3]] 121; EG-DAG: CEIL {{\*? *}}[[RESULT3]] 122; EG-DAG: CEIL {{\*? *}}[[RESULT3]] 123; EG-DAG: CEIL {{\*? *}}[[RESULT4]] 124; EG-DAG: CEIL {{\*? *}}[[RESULT4]] 125; EG-DAG: CEIL {{\*? *}}[[RESULT4]] 126; EG-DAG: CEIL {{\*? *}}[[RESULT4]] 127define void @fceil_v16f32(<16 x float> addrspace(1)* %out, <16 x float> %x) { 128 %y = call <16 x float> @llvm.ceil.v16f32(<16 x float> %x) nounwind readnone 129 store <16 x float> %y, <16 x float> addrspace(1)* %out 130 ret void 131} 132