1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_asm.h"
24 #include "r700_sq.h"
25
r700_bytecode_cf_vtx_build(uint32_t * bytecode,const struct r600_bytecode_cf * cf)26 void r700_bytecode_cf_vtx_build(uint32_t *bytecode, const struct r600_bytecode_cf *cf)
27 {
28 unsigned count = (cf->ndw / 4) - 1;
29 *bytecode++ = S_SQ_CF_WORD0_ADDR(cf->addr >> 1);
30 *bytecode++ = cf->inst |
31 S_SQ_CF_WORD1_BARRIER(1) |
32 S_SQ_CF_WORD1_COUNT(count) |
33 S_SQ_CF_WORD1_COUNT_3(count >> 3);
34 }
35
r700_bytecode_alu_build(struct r600_bytecode * bc,struct r600_bytecode_alu * alu,unsigned id)36 int r700_bytecode_alu_build(struct r600_bytecode *bc, struct r600_bytecode_alu *alu, unsigned id)
37 {
38 bc->bytecode[id++] = S_SQ_ALU_WORD0_SRC0_SEL(alu->src[0].sel) |
39 S_SQ_ALU_WORD0_SRC0_REL(alu->src[0].rel) |
40 S_SQ_ALU_WORD0_SRC0_CHAN(alu->src[0].chan) |
41 S_SQ_ALU_WORD0_SRC0_NEG(alu->src[0].neg) |
42 S_SQ_ALU_WORD0_SRC1_SEL(alu->src[1].sel) |
43 S_SQ_ALU_WORD0_SRC1_REL(alu->src[1].rel) |
44 S_SQ_ALU_WORD0_SRC1_CHAN(alu->src[1].chan) |
45 S_SQ_ALU_WORD0_SRC1_NEG(alu->src[1].neg) |
46 S_SQ_ALU_WORD0_PRED_SEL(alu->pred_sel) |
47 S_SQ_ALU_WORD0_LAST(alu->last);
48
49 /* don't replace gpr by pv or ps for destination register */
50 if (alu->is_op3) {
51 bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
52 S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
53 S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) |
54 S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
55 S_SQ_ALU_WORD1_OP3_SRC2_SEL(alu->src[2].sel) |
56 S_SQ_ALU_WORD1_OP3_SRC2_REL(alu->src[2].rel) |
57 S_SQ_ALU_WORD1_OP3_SRC2_CHAN(alu->src[2].chan) |
58 S_SQ_ALU_WORD1_OP3_SRC2_NEG(alu->src[2].neg) |
59 S_SQ_ALU_WORD1_OP3_ALU_INST(alu->inst) |
60 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle);
61 } else {
62 bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
63 S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
64 S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) |
65 S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
66 S_SQ_ALU_WORD1_OP2_SRC0_ABS(alu->src[0].abs) |
67 S_SQ_ALU_WORD1_OP2_SRC1_ABS(alu->src[1].abs) |
68 S_SQ_ALU_WORD1_OP2_WRITE_MASK(alu->dst.write) |
69 S_SQ_ALU_WORD1_OP2_OMOD(alu->omod) |
70 S_SQ_ALU_WORD1_OP2_ALU_INST(alu->inst) |
71 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle) |
72 S_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(alu->execute_mask) |
73 S_SQ_ALU_WORD1_OP2_UPDATE_PRED(alu->update_pred);
74 }
75 return 0;
76 }
77