1 //===-- SIRegisterInfo.cpp - SI Register Information ---------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the SI implementation of the TargetRegisterInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 15 #include "SIRegisterInfo.h" 16 #include "AMDGPUTargetMachine.h" 17 18 using namespace llvm; 19 SIRegisterInfo(AMDGPUTargetMachine & tm,const TargetInstrInfo & tii)20SIRegisterInfo::SIRegisterInfo(AMDGPUTargetMachine &tm, 21 const TargetInstrInfo &tii) 22 : AMDGPURegisterInfo(tm, tii), 23 TM(tm), 24 TII(tii) 25 { } 26 getReservedRegs(const MachineFunction & MF) const27BitVector SIRegisterInfo::getReservedRegs(const MachineFunction &MF) const 28 { 29 BitVector Reserved(getNumRegs()); 30 return Reserved; 31 } 32 getBinaryCode(unsigned reg) const33unsigned SIRegisterInfo::getBinaryCode(unsigned reg) const 34 { 35 switch (reg) { 36 case AMDGPU::M0: return 124; 37 case AMDGPU::SREG_LIT_0: return 128; 38 default: return getHWRegNum(reg); 39 } 40 } 41 42 const TargetRegisterClass * getISARegClass(const TargetRegisterClass * rc) const43SIRegisterInfo::getISARegClass(const TargetRegisterClass * rc) const 44 { 45 switch (rc->getID()) { 46 case AMDGPU::GPRF32RegClassID: 47 return &AMDGPU::VReg_32RegClass; 48 default: return rc; 49 } 50 } 51 getCFGStructurizerRegClass(MVT VT) const52const TargetRegisterClass * SIRegisterInfo::getCFGStructurizerRegClass( 53 MVT VT) const 54 { 55 switch(VT.SimpleTy) { 56 default: 57 case MVT::i32: return &AMDGPU::VReg_32RegClass; 58 } 59 } 60 #include "SIRegisterGetHWRegNum.inc" 61