1 /**
2 * @file daemon/opd_ibs_trans.c
3 * AMD Instruction Based Sampling (IBS) translation.
4 *
5 * @remark Copyright 2008 - 2010 OProfile authors
6 * @remark Read the file COPYING
7 *
8 * @author Jason Yeh <jason.yeh@amd.com>
9 * @author Paul Drongowski <paul.drongowski@amd.com>
10 * @author Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
11 * Copyright (c) 2008 Advanced Micro Devices, Inc.
12 */
13
14 #include "opd_ibs.h"
15 #include "opd_ibs_macro.h"
16 #include "opd_ibs_trans.h"
17 #include "opd_trans.h"
18 #include "opd_printf.h"
19
20 #include <stdlib.h>
21 #include <stdio.h>
22
23 extern FILE * bta_log;
24 extern FILE * memaccess_log;
25
26 /*
27 * --------------------- FETCH DERIVED FUNCTION
28 */
trans_ibs_fetch(struct transient * trans,unsigned int selected_flag)29 void trans_ibs_fetch (struct transient * trans, unsigned int selected_flag)
30 {
31 struct ibs_fetch_sample * trans_fetch = ((struct ibs_sample*)(trans->ext))->fetch;
32
33 if ((selected_flag) == 0)
34 return;
35
36 CHECK_FETCH_SELECTED_FLAG(DE_IBS_FETCH_ALL) {
37 /* IBS all fetch samples (kills + attempts) */
38 AGG_IBS_EVENT(DE_IBS_FETCH_ALL);
39 }
40
41 CHECK_FETCH_SELECTED_FLAG(DE_IBS_FETCH_KILLED) {
42 /* IBS killed fetches ("case 0") -- All interesting event
43 * flags are clear */
44 if (IBS_FETCH_KILLED(trans_fetch))
45 AGG_IBS_EVENT(DE_IBS_FETCH_KILLED);
46 }
47
48 CHECK_FETCH_SELECTED_FLAG(DE_IBS_FETCH_ATTEMPTED) {
49 /* Any non-killed fetch is an attempted fetch */
50 AGG_IBS_EVENT(DE_IBS_FETCH_ATTEMPTED);
51 }
52
53 CHECK_FETCH_SELECTED_FLAG(DE_IBS_FETCH_COMPLETED) {
54 if (IBS_FETCH_FETCH_COMPLETION(trans_fetch))
55 /* IBS Fetch Completed */
56 AGG_IBS_EVENT(DE_IBS_FETCH_COMPLETED);
57 }
58
59 CHECK_FETCH_SELECTED_FLAG(DE_IBS_FETCH_ABORTED) {
60 if (!IBS_FETCH_FETCH_COMPLETION(trans_fetch))
61 /* IBS Fetch Aborted */
62 AGG_IBS_EVENT(DE_IBS_FETCH_ABORTED);
63 }
64
65 CHECK_FETCH_SELECTED_FLAG(DE_IBS_L1_ITLB_HIT) {
66 /* IBS L1 ITLB hit */
67 if (IBS_FETCH_L1_TLB_HIT(trans_fetch))
68 AGG_IBS_EVENT(DE_IBS_L1_ITLB_HIT);
69 }
70
71 CHECK_FETCH_SELECTED_FLAG(DE_IBS_ITLB_L1M_L2H) {
72 /* IBS L1 ITLB miss and L2 ITLB hit */
73 if (IBS_FETCH_ITLB_L1M_L2H(trans_fetch))
74 AGG_IBS_EVENT(DE_IBS_ITLB_L1M_L2H);
75 }
76
77 CHECK_FETCH_SELECTED_FLAG(DE_IBS_ITLB_L1M_L2M) {
78 /* IBS L1 & L2 ITLB miss; complete ITLB miss */
79 if (IBS_FETCH_ITLB_L1M_L2M(trans_fetch))
80 AGG_IBS_EVENT(DE_IBS_ITLB_L1M_L2M);
81 }
82
83 CHECK_FETCH_SELECTED_FLAG(DE_IBS_IC_MISS) {
84 /* IBS instruction cache miss */
85 if (IBS_FETCH_INST_CACHE_MISS(trans_fetch))
86 AGG_IBS_EVENT(DE_IBS_IC_MISS);
87 }
88
89 CHECK_FETCH_SELECTED_FLAG(DE_IBS_IC_HIT) {
90 /* IBS instruction cache hit */
91 if (IBS_FETCH_INST_CACHE_HIT(trans_fetch))
92 AGG_IBS_EVENT(DE_IBS_IC_HIT);
93 }
94
95 CHECK_FETCH_SELECTED_FLAG(DE_IBS_FETCH_4K_PAGE) {
96 if (IBS_FETCH_PHYS_ADDR_VALID(trans_fetch)
97 && IBS_FETCH_TLB_PAGE_SIZE_4K(trans_fetch))
98 AGG_IBS_EVENT(DE_IBS_FETCH_4K_PAGE);
99 }
100
101 CHECK_FETCH_SELECTED_FLAG(DE_IBS_FETCH_2M_PAGE) {
102 if (IBS_FETCH_PHYS_ADDR_VALID(trans_fetch)
103 && IBS_FETCH_TLB_PAGE_SIZE_2M(trans_fetch))
104 AGG_IBS_EVENT(DE_IBS_FETCH_2M_PAGE);
105 }
106
107 CHECK_FETCH_SELECTED_FLAG(DE_IBS_FETCH_1G_PAGE) {
108 if (IBS_FETCH_PHYS_ADDR_VALID(trans_fetch)
109 && IBS_FETCH_TLB_PAGE_SIZE_1G(trans_fetch))
110 AGG_IBS_EVENT(DE_IBS_FETCH_1G_PAGE);
111 }
112
113 CHECK_FETCH_SELECTED_FLAG(DE_IBS_FETCH_XX_PAGE) {
114 }
115
116 CHECK_FETCH_SELECTED_FLAG(DE_IBS_FETCH_LATENCY) {
117 if (IBS_FETCH_FETCH_LATENCY(trans_fetch))
118 AGG_IBS_COUNT(DE_IBS_FETCH_LATENCY,
119 IBS_FETCH_FETCH_LATENCY(trans_fetch));
120 }
121 }
122
123
124 /*
125 * --------------------- OP DERIVED FUNCTION
126 */
trans_ibs_op(struct transient * trans,unsigned int selected_flag)127 void trans_ibs_op (struct transient * trans, unsigned int selected_flag)
128 {
129 struct ibs_op_sample * trans_op = ((struct ibs_sample*)(trans->ext))->op;
130
131 if ((selected_flag) == 0)
132 return;
133
134 CHECK_OP_SELECTED_FLAG(DE_IBS_OP_ALL) {
135 /* All IBS op samples */
136 AGG_IBS_EVENT(DE_IBS_OP_ALL);
137 }
138
139 CHECK_OP_SELECTED_FLAG(DE_IBS_OP_TAG_TO_RETIRE) {
140 /* Tally retire cycle counts for all sampled macro-ops
141 * IBS tag to retire cycles */
142 if (IBS_OP_TAG_TO_RETIRE_CYCLES(trans_op))
143 AGG_IBS_COUNT(DE_IBS_OP_TAG_TO_RETIRE,
144 IBS_OP_TAG_TO_RETIRE_CYCLES(trans_op));
145 }
146
147 CHECK_OP_SELECTED_FLAG(DE_IBS_OP_COMP_TO_RETIRE) {
148 /* IBS completion to retire cycles */
149 if (IBS_OP_COM_TO_RETIRE_CYCLES(trans_op))
150 AGG_IBS_COUNT(DE_IBS_OP_COMP_TO_RETIRE,
151 IBS_OP_COM_TO_RETIRE_CYCLES(trans_op));
152 }
153
154 CHECK_OP_SELECTED_FLAG(DE_IBS_BRANCH_RETIRED) {
155 if (IBS_OP_BRANCH_RETIRED(trans_op))
156 /* IBS Branch retired op */
157 AGG_IBS_EVENT(DE_IBS_BRANCH_RETIRED) ;
158 }
159
160 CHECK_OP_SELECTED_FLAG(DE_IBS_BRANCH_MISP) {
161 if (IBS_OP_BRANCH_RETIRED(trans_op)
162 /* Test branch-specific event flags */
163 /* IBS mispredicted Branch op */
164 && IBS_OP_BRANCH_MISPREDICT(trans_op))
165 AGG_IBS_EVENT(DE_IBS_BRANCH_MISP) ;
166 }
167
168 CHECK_OP_SELECTED_FLAG(DE_IBS_BRANCH_TAKEN) {
169 if (IBS_OP_BRANCH_RETIRED(trans_op)
170 /* IBS taken Branch op */
171 && IBS_OP_BRANCH_TAKEN(trans_op))
172 AGG_IBS_EVENT(DE_IBS_BRANCH_TAKEN);
173 }
174
175 CHECK_OP_SELECTED_FLAG(DE_IBS_BRANCH_MISP_TAKEN) {
176 if (IBS_OP_BRANCH_RETIRED(trans_op)
177 /* IBS mispredicted taken branch op */
178 && IBS_OP_BRANCH_TAKEN(trans_op)
179 && IBS_OP_BRANCH_MISPREDICT(trans_op))
180 AGG_IBS_EVENT(DE_IBS_BRANCH_MISP_TAKEN);
181 }
182
183 CHECK_OP_SELECTED_FLAG(DE_IBS_RETURN) {
184 if (IBS_OP_BRANCH_RETIRED(trans_op)
185 /* IBS return op */
186 && IBS_OP_RETURN(trans_op))
187 AGG_IBS_EVENT(DE_IBS_RETURN);
188 }
189
190 CHECK_OP_SELECTED_FLAG(DE_IBS_RETURN_MISP) {
191 if (IBS_OP_BRANCH_RETIRED(trans_op)
192 /* IBS mispredicted return op */
193 && IBS_OP_RETURN(trans_op)
194 && IBS_OP_BRANCH_MISPREDICT(trans_op))
195 AGG_IBS_EVENT(DE_IBS_RETURN_MISP);
196 }
197
198 CHECK_OP_SELECTED_FLAG(DE_IBS_RESYNC) {
199 /* Test for a resync macro-op */
200 if (IBS_OP_BRANCH_RESYNC(trans_op))
201 AGG_IBS_EVENT(DE_IBS_RESYNC);
202 }
203 }
204
205
206 /*
207 * --------------------- OP LS DERIVED FUNCTION
208 */
trans_ibs_op_ls(struct transient * trans,unsigned int selected_flag)209 void trans_ibs_op_ls (struct transient * trans, unsigned int selected_flag)
210 {
211 struct ibs_op_sample * trans_op = ((struct ibs_sample*)(trans->ext))->op;
212
213 /* Preliminary check */
214 if (!IBS_OP_IBS_LD_OP(trans_op) && !IBS_OP_IBS_ST_OP(trans_op))
215 return;
216
217
218 if ((selected_flag) == 0)
219 return;
220
221 CHECK_OP_LS_SELECTED_FLAG(DE_IBS_LS_ALL_OP) {
222 /* Count the number of LS op samples */
223 AGG_IBS_EVENT(DE_IBS_LS_ALL_OP) ;
224 }
225
226 CHECK_OP_LS_SELECTED_FLAG(DE_IBS_LS_LOAD_OP) {
227 if (IBS_OP_IBS_LD_OP(trans_op))
228 /* TALLy an IBS load derived event */
229 AGG_IBS_EVENT(DE_IBS_LS_LOAD_OP) ;
230 }
231
232 CHECK_OP_LS_SELECTED_FLAG(DE_IBS_LS_STORE_OP) {
233 if (IBS_OP_IBS_ST_OP(trans_op))
234 /* Count and handle store operations */
235 AGG_IBS_EVENT(DE_IBS_LS_STORE_OP);
236 }
237
238 CHECK_OP_LS_SELECTED_FLAG(DE_IBS_LS_DTLB_L1H) {
239 if (IBS_OP_IBS_DC_LIN_ADDR_VALID(trans_op)
240 && !IBS_OP_IBS_DC_L1_TLB_MISS(trans_op))
241 /* L1 DTLB hit -- This is the most frequent case */
242 AGG_IBS_EVENT(DE_IBS_LS_DTLB_L1H);
243 }
244
245 CHECK_OP_LS_SELECTED_FLAG(DE_IBS_LS_DTLB_L1M_L2H) {
246 /* l2_translation_size = 1 */
247 if (IBS_OP_IBS_DC_LIN_ADDR_VALID(trans_op)
248 && IBS_OP_IBS_DC_L1_TLB_MISS(trans_op)
249 && !IBS_OP_IBS_DC_L2_TLB_MISS(trans_op))
250 /* L1 DTLB miss, L2 DTLB hit */
251 AGG_IBS_EVENT(DE_IBS_LS_DTLB_L1M_L2H);
252 }
253
254 CHECK_OP_LS_SELECTED_FLAG(DE_IBS_LS_DTLB_L1M_L2M) {
255 if (IBS_OP_IBS_DC_LIN_ADDR_VALID(trans_op)
256 && IBS_OP_IBS_DC_L1_TLB_MISS(trans_op)
257 && IBS_OP_IBS_DC_L2_TLB_MISS(trans_op))
258 /* L1 DTLB miss, L2 DTLB miss */
259 AGG_IBS_EVENT(DE_IBS_LS_DTLB_L1M_L2M);
260 }
261
262 CHECK_OP_LS_SELECTED_FLAG(DE_IBS_LS_DC_MISS) {
263 if (IBS_OP_IBS_DC_MISS(trans_op))
264 AGG_IBS_EVENT(DE_IBS_LS_DC_MISS);
265 }
266
267 CHECK_OP_LS_SELECTED_FLAG(DE_IBS_LS_DC_HIT) {
268 if (!IBS_OP_IBS_DC_MISS(trans_op))
269 AGG_IBS_EVENT(DE_IBS_LS_DC_HIT);
270 }
271
272 CHECK_OP_LS_SELECTED_FLAG(DE_IBS_LS_MISALIGNED) {
273 if (IBS_OP_IBS_DC_MISS_ACC(trans_op))
274 AGG_IBS_EVENT(DE_IBS_LS_MISALIGNED);
275 }
276
277 CHECK_OP_LS_SELECTED_FLAG(DE_IBS_LS_BNK_CONF_LOAD) {
278 if (IBS_OP_IBS_DC_LD_BNK_CON(trans_op))
279 AGG_IBS_EVENT(DE_IBS_LS_BNK_CONF_LOAD);
280 }
281
282 CHECK_OP_LS_SELECTED_FLAG(DE_IBS_LS_BNK_CONF_STORE) {
283 if (IBS_OP_IBS_DC_ST_BNK_CON(trans_op))
284 AGG_IBS_EVENT(DE_IBS_LS_BNK_CONF_STORE);
285 }
286
287 CHECK_OP_LS_SELECTED_FLAG(DE_IBS_LS_STL_FORWARDED) {
288 if (IBS_OP_IBS_LD_OP(trans_op)
289 /* Data forwarding info are valid only for load ops */
290 && IBS_OP_IBS_DC_ST_TO_LD_FWD(trans_op))
291 AGG_IBS_EVENT(DE_IBS_LS_STL_FORWARDED) ;
292 }
293
294 CHECK_OP_LS_SELECTED_FLAG(DE_IBS_LS_STL_CANCELLED) {
295 if (IBS_OP_IBS_LD_OP(trans_op))
296 if (IBS_OP_IBS_DC_ST_TO_LD_CAN(trans_op))
297 AGG_IBS_EVENT(DE_IBS_LS_STL_CANCELLED) ;
298 }
299
300 CHECK_OP_LS_SELECTED_FLAG(DE_IBS_LS_UC_MEM_ACCESS) {
301 if (IBS_OP_IBS_DC_UC_MEM_ACC(trans_op))
302 AGG_IBS_EVENT(DE_IBS_LS_UC_MEM_ACCESS);
303 }
304
305 CHECK_OP_LS_SELECTED_FLAG(DE_IBS_LS_WC_MEM_ACCESS) {
306 if (IBS_OP_IBS_DC_WC_MEM_ACC(trans_op))
307 AGG_IBS_EVENT(DE_IBS_LS_WC_MEM_ACCESS);
308 }
309
310 CHECK_OP_LS_SELECTED_FLAG(DE_IBS_LS_LOCKED_OP) {
311 if (IBS_OP_IBS_LOCKED_OP(trans_op))
312 AGG_IBS_EVENT(DE_IBS_LS_LOCKED_OP);
313 }
314
315 CHECK_OP_LS_SELECTED_FLAG(DE_IBS_LS_MAB_HIT) {
316 if (IBS_OP_IBS_DC_MAB_HIT(trans_op))
317 AGG_IBS_EVENT(DE_IBS_LS_MAB_HIT);
318 }
319
320 CHECK_OP_LS_SELECTED_FLAG(DE_IBS_LS_L1_DTLB_4K) {
321 /* l1_translation */
322 if (IBS_OP_IBS_DC_LIN_ADDR_VALID(trans_op)
323 && !IBS_OP_IBS_DC_L1_TLB_MISS(trans_op)
324
325 && !IBS_OP_IBS_DC_L1_TLB_HIT_2MB(trans_op)
326 && !IBS_OP_IBS_DC_L1_TLB_HIT_1GB(trans_op))
327 /* This is the most common case, unfortunately */
328 AGG_IBS_EVENT(DE_IBS_LS_L1_DTLB_4K) ;
329 }
330
331 CHECK_OP_LS_SELECTED_FLAG(DE_IBS_LS_L1_DTLB_2M) {
332 /* l1_translation */
333 if (IBS_OP_IBS_DC_LIN_ADDR_VALID(trans_op)
334 && !IBS_OP_IBS_DC_L1_TLB_MISS(trans_op)
335
336 && IBS_OP_IBS_DC_L1_TLB_HIT_2MB(trans_op))
337 /* 2M L1 DTLB page translation */
338 AGG_IBS_EVENT(DE_IBS_LS_L1_DTLB_2M);
339 }
340
341 CHECK_OP_LS_SELECTED_FLAG(DE_IBS_LS_L1_DTLB_1G) {
342 /* l1_translation */
343 if (IBS_OP_IBS_DC_LIN_ADDR_VALID(trans_op)
344 && !IBS_OP_IBS_DC_L1_TLB_MISS(trans_op)
345
346 && !IBS_OP_IBS_DC_L1_TLB_HIT_2MB(trans_op)
347 && IBS_OP_IBS_DC_L1_TLB_HIT_1GB(trans_op))
348 /* 1G L1 DTLB page translation */
349 AGG_IBS_EVENT(DE_IBS_LS_L1_DTLB_1G);
350 }
351
352 CHECK_OP_LS_SELECTED_FLAG(DE_IBS_LS_L1_DTLB_RES) {
353 }
354
355 CHECK_OP_LS_SELECTED_FLAG(DE_IBS_LS_L2_DTLB_4K) {
356 /* l2_translation_size = 1 */
357 if (IBS_OP_IBS_DC_LIN_ADDR_VALID(trans_op)
358 && IBS_OP_IBS_DC_L1_TLB_MISS(trans_op)
359 && !IBS_OP_IBS_DC_L2_TLB_MISS(trans_op)
360
361 /* L2 DTLB page translation */
362 && !IBS_OP_IBS_DC_L2_TLB_HIT_2MB(trans_op)
363 && !IBS_OP_IBS_DC_L2_TLB_HIT_1GB(trans_op))
364 /* 4K L2 DTLB page translation */
365 AGG_IBS_EVENT(DE_IBS_LS_L2_DTLB_4K);
366 }
367
368 CHECK_OP_LS_SELECTED_FLAG(DE_IBS_LS_L2_DTLB_2M) {
369 /* l2_translation_size = 1 */
370 if (IBS_OP_IBS_DC_LIN_ADDR_VALID(trans_op)
371 && IBS_OP_IBS_DC_L1_TLB_MISS(trans_op)
372 && !IBS_OP_IBS_DC_L2_TLB_MISS(trans_op)
373
374 /* L2 DTLB page translation */
375 && IBS_OP_IBS_DC_L2_TLB_HIT_2MB(trans_op)
376 && !IBS_OP_IBS_DC_L2_TLB_HIT_1GB(trans_op))
377 /* 2M L2 DTLB page translation */
378 AGG_IBS_EVENT(DE_IBS_LS_L2_DTLB_2M);
379 }
380
381 CHECK_OP_LS_SELECTED_FLAG(DE_IBS_LS_L2_DTLB_1G) {
382 /* l2_translation_size = 1 */
383 if (IBS_OP_IBS_DC_LIN_ADDR_VALID(trans_op)
384 && IBS_OP_IBS_DC_L1_TLB_MISS(trans_op)
385 && !IBS_OP_IBS_DC_L2_TLB_MISS(trans_op)
386
387 /* L2 DTLB page translation */
388 && !IBS_OP_IBS_DC_L2_TLB_HIT_2MB(trans_op)
389 && IBS_OP_IBS_DC_L2_TLB_HIT_1GB(trans_op))
390 /* 2M L2 DTLB page translation */
391 AGG_IBS_EVENT(DE_IBS_LS_L2_DTLB_1G);
392 }
393
394 CHECK_OP_LS_SELECTED_FLAG(DE_IBS_LS_L2_DTLB_RES2) {
395 }
396
397 CHECK_OP_LS_SELECTED_FLAG(DE_IBS_LS_DC_LOAD_LAT) {
398 if (IBS_OP_IBS_LD_OP(trans_op)
399 /* If the load missed in DC, tally the DC load miss latency */
400 && IBS_OP_IBS_DC_MISS(trans_op))
401 /* DC load miss latency is only reliable for load ops */
402 AGG_IBS_COUNT(DE_IBS_LS_DC_LOAD_LAT,
403 IBS_OP_DC_MISS_LATENCY(trans_op)) ;
404 }
405 }
406
407 /*
408 * --------------------- OP NB DERIVED FUNCTION
409 *
410 * NB data is only guaranteed reliable for load operations
411 * that miss in L1 and L2 cache. NB data arrives too late
412 * to be reliable for store operations
413 */
trans_ibs_op_nb(struct transient * trans,unsigned int selected_flag)414 void trans_ibs_op_nb (struct transient * trans, unsigned int selected_flag)
415 {
416 struct ibs_op_sample * trans_op = ((struct ibs_sample*)(trans->ext))->op;
417
418 /* Preliminary check */
419 if ((selected_flag) == 0)
420 return;
421
422 if (!IBS_OP_IBS_LD_OP(trans_op))
423 return;
424
425 if (!IBS_OP_IBS_DC_MISS(trans_op))
426 return;
427
428 if (IBS_OP_NB_IBS_REQ_SRC(trans_op) == 0)
429 return;
430
431 CHECK_OP_NB_SELECTED_FLAG(DE_IBS_NB_LOCAL) {
432 if (!IBS_OP_NB_IBS_REQ_DST_PROC(trans_op))
433 /* Request was serviced by local processor */
434 AGG_IBS_EVENT(DE_IBS_NB_LOCAL) ;
435 }
436
437 CHECK_OP_NB_SELECTED_FLAG(DE_IBS_NB_REMOTE) {
438 if (IBS_OP_NB_IBS_REQ_DST_PROC(trans_op))
439 /* Request was serviced by remote processor */
440 AGG_IBS_EVENT(DE_IBS_NB_REMOTE) ;
441 }
442
443 CHECK_OP_NB_SELECTED_FLAG(DE_IBS_NB_LOCAL_L3) {
444 if (!IBS_OP_NB_IBS_REQ_DST_PROC(trans_op)
445 && IBS_OP_NB_IBS_REQ_SRC_01(trans_op))
446 AGG_IBS_EVENT(DE_IBS_NB_LOCAL_L3);
447 }
448
449 CHECK_OP_NB_SELECTED_FLAG(DE_IBS_NB_LOCAL_CACHE) {
450 if (!IBS_OP_NB_IBS_REQ_DST_PROC(trans_op)
451 && IBS_OP_NB_IBS_REQ_SRC_02(trans_op))
452 AGG_IBS_EVENT(DE_IBS_NB_LOCAL_CACHE);
453 }
454
455 CHECK_OP_NB_SELECTED_FLAG(DE_IBS_NB_REMOTE_CACHE) {
456 if (IBS_OP_NB_IBS_REQ_DST_PROC(trans_op)
457 && IBS_OP_NB_IBS_REQ_SRC_02(trans_op))
458 AGG_IBS_EVENT(DE_IBS_NB_REMOTE_CACHE) ;
459 }
460
461 CHECK_OP_NB_SELECTED_FLAG(DE_IBS_NB_LOCAL_DRAM) {
462 if (!IBS_OP_NB_IBS_REQ_DST_PROC(trans_op)
463 && IBS_OP_NB_IBS_REQ_SRC_03(trans_op))
464 AGG_IBS_EVENT(DE_IBS_NB_LOCAL_DRAM);
465 }
466
467 CHECK_OP_NB_SELECTED_FLAG(DE_IBS_NB_REMOTE_DRAM) {
468 if (IBS_OP_NB_IBS_REQ_DST_PROC(trans_op)
469 && IBS_OP_NB_IBS_REQ_SRC_03(trans_op))
470 AGG_IBS_EVENT(DE_IBS_NB_REMOTE_DRAM) ;
471 }
472
473 CHECK_OP_NB_SELECTED_FLAG(DE_IBS_NB_LOCAL_OTHER) {
474 if (!IBS_OP_NB_IBS_REQ_DST_PROC(trans_op)
475 && IBS_OP_NB_IBS_REQ_SRC_07(trans_op))
476 AGG_IBS_EVENT(DE_IBS_NB_LOCAL_OTHER);
477 }
478
479 CHECK_OP_NB_SELECTED_FLAG(DE_IBS_NB_REMOTE_OTHER) {
480 if (IBS_OP_NB_IBS_REQ_DST_PROC(trans_op)
481 && IBS_OP_NB_IBS_REQ_SRC_07(trans_op))
482 AGG_IBS_EVENT(DE_IBS_NB_REMOTE_OTHER) ;
483 }
484
485 CHECK_OP_NB_SELECTED_FLAG(DE_IBS_NB_CACHE_STATE_M) {
486 if (IBS_OP_NB_IBS_REQ_SRC_02(trans_op)
487 && !IBS_OP_NB_IBS_CACHE_HIT_ST(trans_op))
488 AGG_IBS_EVENT(DE_IBS_NB_CACHE_STATE_M) ;
489 }
490
491 CHECK_OP_NB_SELECTED_FLAG(DE_IBS_NB_CACHE_STATE_O) {
492 if (IBS_OP_NB_IBS_REQ_SRC_02(trans_op)
493 && IBS_OP_NB_IBS_CACHE_HIT_ST(trans_op))
494 AGG_IBS_EVENT(DE_IBS_NB_CACHE_STATE_O) ;
495 }
496
497 CHECK_OP_NB_SELECTED_FLAG(DE_IBS_NB_LOCAL_LATENCY) {
498 if (!IBS_OP_NB_IBS_REQ_DST_PROC(trans_op))
499 /* Request was serviced by local processor */
500 AGG_IBS_COUNT(DE_IBS_NB_LOCAL_LATENCY,
501 IBS_OP_DC_MISS_LATENCY(trans_op));
502 }
503
504 CHECK_OP_NB_SELECTED_FLAG(DE_IBS_NB_REMOTE_LATENCY) {
505 if (IBS_OP_NB_IBS_REQ_DST_PROC(trans_op))
506 /* Request was serviced by remote processor */
507 AGG_IBS_COUNT(DE_IBS_NB_REMOTE_LATENCY,
508 IBS_OP_DC_MISS_LATENCY(trans_op));
509 }
510 }
511
512
trans_ibs_op_rip_invalid(struct transient * trans)513 int trans_ibs_op_rip_invalid (struct transient * trans)
514 {
515 struct ibs_op_sample * trans_op = ((struct ibs_sample*)(trans->ext))->op;
516
517 if (IBS_OP_RIP_INVALID(trans_op))
518 return 1;
519
520 return 0;
521 }
522
523
trans_ibs_op_mask_reserved(unsigned int family,struct transient * trans)524 void trans_ibs_op_mask_reserved (unsigned int family, struct transient * trans)
525 {
526 struct ibs_op_sample * trans_op = ((struct ibs_sample*)(trans->ext))->op;
527
528 switch (family) {
529 case 0x10:
530 /* Reserved IbsRipInvalid (MSRC001_1035[38])*/
531 trans_op->ibs_op_data1_high &= ~MASK_RIP_INVALID;
532 break;
533 case 0x12:
534 /* Reserved NbIbsReqDstProc (MSRCC001_1036[4]) */
535 trans_op->ibs_op_data2_low &= ~NB_MASK_REQ_DST_PROC;
536 /* Reserved NbIbsReqCacheHitSt (MSRCC001_1036[5]) */
537 trans_op->ibs_op_data2_low &= ~NB_MASK_L3_STATE;
538 break;
539 case 0x14:
540 /* Reserved NbIbsReqDstProc (MSRCC001_1036[4]) */
541 trans_op->ibs_op_data2_low &= ~NB_MASK_REQ_DST_PROC;
542 /* Reserved NbIbsReqCacheHitSt (MSRCC001_1036[5]) */
543 trans_op->ibs_op_data2_low &= ~NB_MASK_L3_STATE;
544 /* Reserved IbsDcL1tlbHit1G (MSRC001_1037[5]) */
545 trans_op->ibs_op_data3_low &= ~DC_MASK_L1_HIT_1G;
546 /* Reserved IbsDcLdBnkCon (MSRC001_1037[9]) */
547 trans_op->ibs_op_data3_low &= ~DC_MASK_LD_BANK_CONFLICT;
548 /* Reserved IbsDcStBnkCon (MSRC001_1037[10]) */
549 trans_op->ibs_op_data3_low &= ~DC_MASK_ST_BANK_CONFLICT;
550 /* Reserved IbsDcStToLdCan (MSRC001_1037[12]) */
551 trans_op->ibs_op_data3_low &= ~DC_MASK_ST_TO_LD_CANCEL;
552 /* Reserved IbsDcL2tlbHit1G (MSRC001_1037[19]) */
553 trans_op->ibs_op_data3_low &= ~DC_MASK_L2_HIT_1G;
554
555 break;
556 case 0x15:
557 default:
558 break;
559
560 }
561 }
562
563
trans_ibs_op_bta(struct transient * trans)564 void trans_ibs_op_bta(struct transient * trans)
565 {
566 static cookie_t old_cookie = NO_COOKIE;
567 static cookie_t old_app_cookie = NO_COOKIE;
568 static char const * mod = NULL;
569 static char const * app = NULL;
570 const char vmlinux[10] = "vmlinux";
571 struct ibs_op_sample * trans_op = ((struct ibs_sample*)(trans->ext))->op;
572
573 if (!bta_log)
574 return;
575
576 if (!trans_op->ibs_op_brtgt_addr)
577 return;
578
579 if( old_app_cookie == INVALID_COOKIE
580 || old_app_cookie == NO_COOKIE
581 || old_app_cookie != trans->app_cookie) {
582 app = find_cookie(trans->app_cookie);
583 old_app_cookie = trans->cookie;
584 }
585
586 if (trans->in_kernel == 1) {
587 mod = vmlinux;
588 old_cookie = NO_COOKIE;
589 } else {
590 if( old_cookie == INVALID_COOKIE
591 || old_cookie == NO_COOKIE
592 || old_cookie != trans->cookie) {
593 mod = find_cookie(trans->cookie);
594 old_cookie = trans->cookie;
595 }
596 }
597
598 fprintf(bta_log, "0x%016llx,0x%016llx,%02lu %08u,%08u,0x%08x,0x%08lx\n",
599 trans->app_cookie, trans->cookie, trans->cpu, trans->tgid, trans->tid, (unsigned int)trans->pc,
600 trans_op->ibs_op_brtgt_addr);
601 }
602
603
trans_ibs_op_ls_memaccess(struct transient * trans)604 void trans_ibs_op_ls_memaccess(struct transient * trans)
605 {
606 static cookie_t old_cookie = NO_COOKIE;
607 static cookie_t old_app_cookie = NO_COOKIE;
608 static char const * mod = NULL;
609 static char const * app = NULL;
610 const char vmlinux[10] = "vmlinux";
611 struct ibs_op_sample * trans_op = ((struct ibs_sample*)(trans->ext))->op;
612
613 if (!memaccess_log)
614 return;
615
616 if( old_app_cookie == INVALID_COOKIE
617 || old_app_cookie == NO_COOKIE
618 || old_app_cookie != trans->app_cookie) {
619 app = find_cookie(trans->app_cookie);
620 old_app_cookie = trans->cookie;
621 }
622
623 if (trans->in_kernel == 1) {
624 mod = vmlinux;
625 old_cookie = NO_COOKIE;
626 } else {
627 if( old_cookie == INVALID_COOKIE
628 || old_cookie == NO_COOKIE
629 || old_cookie != trans->cookie) {
630 mod = find_cookie(trans->cookie);
631 old_cookie = trans->cookie;
632 }
633 }
634
635 fprintf(memaccess_log, "0x%016llx,0x%016llx,%02lu,%08u,%08u,0x%08x,0x%08u:%08x,0x%08x:%08x,%s,%08u\n",
636 trans->app_cookie,
637 trans->cookie,
638 trans->cpu,
639 trans->tgid,
640 trans->tid,
641 (unsigned int)trans->pc,
642 trans_op->ibs_op_phys_addr_high, trans_op->ibs_op_phys_addr_low,
643 trans_op->ibs_op_ldst_linaddr_high, trans_op->ibs_op_ldst_linaddr_low,
644 (IBS_OP_IBS_LD_OP(trans_op))? "LD": "ST",
645 (unsigned int) IBS_OP_DC_MISS_LATENCY(trans_op));
646 }
647