/external/llvm/test/CodeGen/R600/ |
D | unsupported-cc.ll | 30 ; CHECK: SETGE * T{{[0-9]}}.[[CHAN:[XYZW]]], KC0[2].Z, literal.x 43 ; CHECK: SETGE T{{[0-9]\.[XYZW]}}, KC0[2].Z, literal.x 116 ; CHECK: SETGE T{{[0-9]\.[XYZW]}}, literal.x, KC0[2].Z
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D | llvm.round.ll | 20 ; R600-DAG: SETGE
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D | setcc.ll | 143 ; R600: SETGE 170 ; R600: SETGE
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/external/llvm/include/llvm/CodeGen/ |
D | ISDOpcodes.h | 801 SETGE, // 1 X 0 1 1 True if greater than or equal enumerator 813 return Code == SETGT || Code == SETGE || Code == SETLT || Code == SETLE; in isSignedIntSetCC()
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/external/mesa3d/src/gallium/drivers/radeon/ |
D | AMDGPUISelLowering.cpp | 236 ISD::SETGE); in LowerUDIVREM() 242 ISD::SETGE); in LowerUDIVREM()
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D | AMDGPUInstructions.td | 60 case ISD::SETGE: return true;}}}]
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D | R600Instructions.td | 286 0xA, "SETGE", 423 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETGE))]
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/external/llvm/lib/Target/X86/ |
D | X86IntrinsicsInfo.h | 507 X86_INTRINSIC_DATA(sse2_comige_sd, COMI, X86ISD::COMI, ISD::SETGE), 547 X86_INTRINSIC_DATA(sse2_ucomige_sd, COMI, X86ISD::UCOMI, ISD::SETGE), 580 X86_INTRINSIC_DATA(sse_comige_ss, COMI, X86ISD::COMI, ISD::SETGE), 589 X86_INTRINSIC_DATA(sse_ucomige_ss, COMI, X86ISD::UCOMI, ISD::SETGE),
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D | X86InstrCMovSetCC.td | 109 defm SETGE : SETCC<0x9D, "setge", X86_COND_GE>; // signed greater or equal
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/external/llvm/lib/CodeGen/ |
D | Analysis.cpp | 190 case ISD::SETOGE: case ISD::SETUGE: return ISD::SETGE; in getFCmpCodeWithoutNaN() 204 case ICmpInst::ICMP_SGE: return ISD::SETGE; in getICmpCondCode()
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D | TargetLoweringBase.cpp | 715 CCs[RTLIB::OGE_F32] = ISD::SETGE; in InitCmpLibcallCCs() 716 CCs[RTLIB::OGE_F64] = ISD::SETGE; in InitCmpLibcallCCs() 717 CCs[RTLIB::OGE_F128] = ISD::SETGE; in InitCmpLibcallCCs()
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/external/llvm/lib/Target/Hexagon/ |
D | HexagonSelectCCInfo.td | 63 IntRegs:$fval, SETGE)),
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/external/llvm/lib/Target/PowerPC/ |
D | PPCInstrQPX.td | 1027 def : Pat<(setcc v4f64:$FRA, v4f64:$FRB, SETGE), 1074 def : Pat<(setcc v4f32:$FRA, v4f32:$FRB, SETGE), 1123 def : Pat<(v4f64 (selectcc i1:$lhs, i1:$rhs, v4f64:$tval, v4f64:$fval, SETGE)), 1136 def : Pat<(v4f32 (selectcc i1:$lhs, i1:$rhs, v4f32:$tval, v4f32:$fval, SETGE)), 1149 def : Pat<(v4i1 (selectcc i1:$lhs, i1:$rhs, v4i1:$tval, v4i1:$fval, SETGE)),
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D | PPCInstrInfo.td | 2806 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGE)), 2901 defm : ExtSetCCPat<SETGE, 2933 defm : ExtSetCCPat<SETGE, 2988 defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGE)), 3016 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETGE)), 3056 defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGE)), 3084 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETGE)), 3111 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETGE)), 3142 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETGE)), 3172 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGE)), [all …]
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D | PPCISelDAGToDAG.cpp | 2048 case ISD::SETGE: return PPC::PRED_GE; in getPredicateForSetCC() 2072 case ISD::SETGE: Invert = true; return 0; // !Bit #0 = SETUGE in getCRIdxForSetCC() 2100 case ISD::SETLE: CC = ISD::SETGE; Swap = true; break; in getVCmpInst() 2132 case ISD::SETGE: in getVCmpInst() 2146 case ISD::SETGE: CC = ISD::SETLE; Swap = true; break; in getVCmpInst()
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D | PPCInstrVSX.td | 917 def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETGE)), 930 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGE)),
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/external/llvm/lib/Target/R600/ |
D | AMDGPUInstructions.td | 86 [{return N->get() == ISD::SETOGE || N->get() == ISD::SETGE;}] 126 def COND_SGE : PatLeaf <(cond), [{return N->get() == ISD::SETGE;}]>;
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D | R600Instructions.td | 706 0xA, "SETGE", 801 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETGE))] 1667 def : CND_INT_f32 <CNDGE_INT, SETGE>;
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/external/llvm/lib/CodeGen/SelectionDAG/ |
D | TargetLowering.cpp | 140 case ISD::SETGE: in softenSetCCOperands() 1424 case ISD::SETGE: in SimplifySetCC() 1587 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { in SimplifySetCC() 1591 ISD::CondCode NewCC = (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT; in SimplifySetCC() 1619 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal) in SimplifySetCC() 2005 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y in SimplifySetCC()
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D | LegalizeIntegerTypes.cpp | 928 case ISD::SETGE: in PromoteSetCCOperands() 2073 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE); in ExpandIntRes_SADDSUBO() 2074 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE); in ExpandIntRes_SADDSUBO() 2079 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE); in ExpandIntRes_SADDSUBO() 2605 case ISD::SETGE: in IntegerExpandSetCCOperands() 2638 (CCCode == ISD::SETLE || CCCode == ISD::SETGE || in IntegerExpandSetCCOperands()
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D | SelectionDAGDumper.cpp | 323 case ISD::SETGE: return "setge"; in getOperationName()
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/external/llvm/lib/Target/BPF/ |
D | BPFISelLowering.cpp | 591 case ISD::SETGE: in EmitInstrWithCustomInserter()
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D | BPFInstrInfo.td | 72 [{return (N->getZExtValue() == ISD::SETGE);}]>;
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/external/llvm/lib/Target/ARM/ |
D | ARMISelLowering.cpp | 1223 case ISD::SETGE: return ARMCC::GE; in IntCCToARMCC() 1243 case ISD::SETGE: in FPCCToARMCC() 3158 case ISD::SETGE: in getARMCmp() 3174 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE; in getARMCmp() 3527 if (CC == ISD::SETGT || CC == ISD::SETGE) in LowerSELECT_CC() 3534 if (CC == ISD::SETGT || CC == ISD::SETGE) in LowerSELECT_CC() 4091 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE, in LowerShiftRightParts() 4125 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE, in LowerShiftLeftParts() 4374 case ISD::SETGE: Opc = ARMISD::VCGE; break; in LowerVSETCC() 4407 case ISD::SETGE: Opc = ARMISD::VCGE; break; in LowerVSETCC() [all …]
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/external/llvm/include/llvm/Target/ |
D | TargetSelectionDAG.td | 544 def SETEQ : CondCode; def SETGT : CondCode; def SETGE : CondCode; 907 (setcc node:$lhs, node:$rhs, SETGE)>;
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