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Searched refs:SETLT (Results 1 – 25 of 37) sorted by relevance

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/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h802 SETLT, // 1 X 1 0 0 True if less than enumerator
813 return Code == SETGT || Code == SETGE || Code == SETLT || Code == SETLE; in isSignedIntSetCC()
/external/llvm/lib/Target/Hexagon/
DHexagonSelectCCInfo.td43 IntRegs:$fval, SETLT)),
113 DoubleRegs:$fval, SETLT)),
/external/mesa3d/src/gallium/drivers/radeon/
DAMDILISelLowering.cpp601 ISD::SETLT); in LowerSDIV32()
608 ISD::SETLT); in LowerSDIV32()
707 SDValue r10 = DAG.getSetCC(DL, OVT, r0, DAG.getConstant(0, OVT), ISD::SETLT); in LowerSREM32()
710 SDValue r11 = DAG.getSetCC(DL, OVT, r1, DAG.getConstant(0, OVT), ISD::SETLT); in LowerSREM32()
DAMDGPUInstructions.td67 case ISD::SETLT: return true;}}}]
/external/llvm/lib/Target/X86/
DX86IntrinsicsInfo.h510 X86_INTRINSIC_DATA(sse2_comilt_sd, COMI, X86ISD::COMI, ISD::SETLT),
550 X86_INTRINSIC_DATA(sse2_ucomilt_sd, COMI, X86ISD::UCOMI, ISD::SETLT),
583 X86_INTRINSIC_DATA(sse_comilt_ss, COMI, X86ISD::COMI, ISD::SETLT),
592 X86_INTRINSIC_DATA(sse_ucomilt_ss, COMI, X86ISD::UCOMI, ISD::SETLT),
/external/llvm/lib/CodeGen/
DAnalysis.cpp187 case ISD::SETOLT: case ISD::SETULT: return ISD::SETLT; in getFCmpCodeWithoutNaN()
206 case ICmpInst::ICMP_SLT: return ISD::SETLT; in getICmpCondCode()
DTargetLoweringBase.cpp718 CCs[RTLIB::OLT_F32] = ISD::SETLT; in InitCmpLibcallCCs()
719 CCs[RTLIB::OLT_F64] = ISD::SETLT; in InitCmpLibcallCCs()
720 CCs[RTLIB::OLT_F128] = ISD::SETLT; in InitCmpLibcallCCs()
/external/llvm/lib/CodeGen/SelectionDAG/
DTargetLowering.cpp145 case ISD::SETLT: in softenSetCCOperands()
1427 case ISD::SETLT: in SimplifySetCC()
1606 ISD::CondCode NewCC = (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT; in SimplifySetCC()
1617 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal) in SimplifySetCC()
1630 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal) in SimplifySetCC()
1634 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1) in SimplifySetCC()
1652 ISD::SETLT); in SimplifySetCC()
1997 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X in SimplifySetCC()
2968 DAG.getConstant(0, NVT), Ret, ISD::SETLT); in expandFP_TO_SINT()
DSelectionDAGDumper.cpp324 case ISD::SETLT: return "setlt"; in getOperationName()
DLegalizeIntegerTypes.cpp930 case ISD::SETLT: in PromoteSetCCOperands()
2588 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0 in IntegerExpandSetCCOperands()
2599 case ISD::SETLT: in IntegerExpandSetCCOperands()
2641 (CCCode == ISD::SETLT || CCCode == ISD::SETGT || in IntegerExpandSetCCOperands()
2876 ISD::SETLT); in ExpandIntOp_UINT_TO_FP()
DLegalizeDAG.cpp1609 ISD::SETLT); in ExpandFCOPYSIGN()
1733 case ISD::SETLT: in LegalizeSetCCCondCode()
2523 Op0, DAG.getConstant(0, MVT::i64), ISD::SETLT); in ExpandLegalINT_TO_FP()
2562 ISD::SETLT); in ExpandLegalINT_TO_FP()
3057 Tmp1, ISD::SETLT); in ExpandNode()
/external/llvm/lib/Target/PowerPC/
DPPCInstrQPX.td1030 def : Pat<(setcc v4f64:$FRA, v4f64:$FRB, SETLT),
1077 def : Pat<(setcc v4f32:$FRA, v4f32:$FRB, SETLT),
1117 def : Pat<(v4f64 (selectcc i1:$lhs, i1:$rhs, v4f64:$tval, v4f64:$fval, SETLT)),
1130 def : Pat<(v4f32 (selectcc i1:$lhs, i1:$rhs, v4f32:$tval, v4f32:$fval, SETLT)),
1143 def : Pat<(v4i1 (selectcc i1:$lhs, i1:$rhs, v4i1:$tval, v4i1:$fval, SETLT)),
DPPCInstrInfo.td2796 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLT)),
2893 defm : ExtSetCCPat<SETLT,
2925 defm : ExtSetCCPat<SETLT,
2960 def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLT)),
3005 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETLT)),
3028 def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLT)),
3073 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETLT)),
3096 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETLT)),
3127 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETLT)),
3163 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLT)),
[all …]
DPPCISelDAGToDAG.cpp2042 case ISD::SETLT: return PPC::PRED_LT; in getPredicateForSetCC()
2065 case ISD::SETLT: return 0; // Bit #0 = SETOLT in getCRIdxForSetCC()
2101 case ISD::SETLT: CC = ISD::SETGT; Swap = true; break; in getVCmpInst()
2147 case ISD::SETLT: CC = ISD::SETGT; Swap = true; break; in getVCmpInst()
2229 case ISD::SETLT: { in SelectSETCC()
2262 case ISD::SETLT: { in SelectSETCC()
DPPCInstrVSX.td911 def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETLT)),
924 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLT)),
/external/llvm/lib/Target/R600/
DAMDGPUInstructions.td91 [{return N->get() == ISD::SETOLT || N->get() == ISD::SETLT;}]
127 def COND_SLT : PatLeaf <(cond), [{return N->get() == ISD::SETLT;}]>;
DAMDGPUISelLowering.cpp1107 case ISD::SETLT: { in CombineFMinMaxLegacy()
1167 case ISD::SETLT: { in CombineIMinMax()
1867 SDValue LHSign = DAG.getSelectCC(DL, LHS, Zero, NegOne, Zero, ISD::SETLT); in LowerSDIVREM()
1868 SDValue RHSign = DAG.getSelectCC(DL, RHS, Zero, NegOne, Zero, ISD::SETLT); in LowerSDIVREM()
1985 SDValue ExpLt0 = DAG.getSetCC(SL, SetCCVT, Exp, Zero, ISD::SETLT); in LowerFTRUNC()
2089 SDValue ExpLt0 = DAG.getSetCC(SL, SetCCVT, Exp, Zero, ISD::SETLT); in LowerFROUND64()
DR600ISelLowering.cpp48 setCondCodeAction(ISD::SETLT, MVT::f32, Expand); in R600TargetLowering()
60 setCondCodeAction(ISD::SETLT, MVT::i32, Expand); in R600TargetLowering()
/external/llvm/lib/Target/BPF/
DBPFISelLowering.cpp471 case ISD::SETLT: in NegateCC()
/external/llvm/lib/Target/Mips/
DMipsSEISelLowering.cpp957 case ISD::SETLT: in isLegalDSPCondCode()
1006 if (CondCode == ISD::SETLT || CondCode == ISD::SETLE) in performVSELECTCombine()
1714 Op->getOperand(2), ISD::SETLT); in lowerINTRINSIC_WO_CHAIN()
1720 lowerMSASplatImm(Op, 2, DAG), ISD::SETLT); in lowerINTRINSIC_WO_CHAIN()
DMipsDSPInstrInfo.td1361 def : DSPSetCCPat<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETLT>;
1374 def : DSPSelectCCPat<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETLT>;
/external/llvm/include/llvm/Target/
DTargetSelectionDAG.td545 def SETLT : CondCode; def SETLE : CondCode; def SETNE : CondCode;
909 (setcc node:$lhs, node:$rhs, SETLT)>;
/external/llvm/lib/Target/AArch64/
DAArch64ISelLowering.cpp1006 case ISD::SETLT: in changeIntCCToAArch64CC()
1067 case ISD::SETLT: in changeFPCCToAArch64CC()
1175 case ISD::SETLT: in getAArch64Cmp()
1181 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT; in getAArch64Cmp()
1202 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE; in getAArch64Cmp()
3316 } else if (CC == ISD::SETLT && LHS.getOpcode() != ISD::AND) { in LowerBR_CC()
3716 case ISD::SETLT: in LowerSELECT_CC()
6940 SDValue Cmp = getAArch64Cmp(N0, Zero, ISD::SETLT, CCVal, DAG, DL); in BuildSDIVPow2()
/external/llvm/lib/Target/ARM/
DARMISelLowering.cpp1224 case ISD::SETLT: return ARMCC::LT; in IntCCToARMCC()
1253 case ISD::SETLT: in FPCCToARMCC()
3157 case ISD::SETLT: in getARMCmp()
3160 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT; in getARMCmp()
3174 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE; in getARMCmp()
3529 if (CC == ISD::SETLT || CC == ISD::SETLE) in LowerSELECT_CC()
3532 if (CC == ISD::SETLT || CC == ISD::SETLE) in LowerSELECT_CC()
4368 case ISD::SETLT: Swap = true; // Fallthrough in LowerVSETCC()
4404 case ISD::SETLT: Swap = true; in LowerVSETCC()
9682 case ISD::SETLT: in PerformSELECT_CCCombine()
/external/llvm/lib/Target/MSP430/
DMSP430ISelLowering.cpp880 case ISD::SETLT: in EmitCMP()

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