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Searched refs:SUBREG_TO_REG (Results 1 – 25 of 30) sorted by relevance

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/external/llvm/lib/Target/AArch64/
DAArch64InstrAtomics.td221 (SUBREG_TO_REG (i64 0), (LDXRB GPR64sp:$addr), sub_32)>;
223 (SUBREG_TO_REG (i64 0), (LDXRH GPR64sp:$addr), sub_32)>;
225 (SUBREG_TO_REG (i64 0), (LDXRW GPR64sp:$addr), sub_32)>;
229 (SUBREG_TO_REG (i64 0), (LDXRB GPR64sp:$addr), sub_32)>;
231 (SUBREG_TO_REG (i64 0), (LDXRH GPR64sp:$addr), sub_32)>;
233 (SUBREG_TO_REG (i64 0), (LDXRW GPR64sp:$addr), sub_32)>;
254 (SUBREG_TO_REG (i64 0), (LDAXRB GPR64sp:$addr), sub_32)>;
256 (SUBREG_TO_REG (i64 0), (LDAXRH GPR64sp:$addr), sub_32)>;
258 (SUBREG_TO_REG (i64 0), (LDAXRW GPR64sp:$addr), sub_32)>;
262 (SUBREG_TO_REG (i64 0), (LDAXRB GPR64sp:$addr), sub_32)>;
[all …]
DAArch64InstrInfo.td505 (SUBREG_TO_REG (i64 0), (MOVi32imm (trunc_imm imm:$src)), sub_32)>;
1295 (SUBREG_TO_REG (i64 0),
1300 (SUBREG_TO_REG (i64 0),
1455 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;
1457 (SUBREG_TO_REG (i64 0), (LDRHHui GPR64sp:$Rn, uimm12s2:$offset), sub_32)>;
1463 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;
1473 (SUBREG_TO_REG (i64 0), (LDRWui GPR64sp:$Rn, uimm12s4:$offset), sub_32)>;
1475 (SUBREG_TO_REG (i64 0), (LDRHHui GPR64sp:$Rn, uimm12s2:$offset), sub_32)>;
1477 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;
1479 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;
[all …]
DAArch64FastISel.cpp1801 TII.get(AArch64::SUBREG_TO_REG), Reg64) in emitLoad()
3832 TII.get(AArch64::SUBREG_TO_REG), Reg64) in emiti1Ext()
3985 TII.get(AArch64::SUBREG_TO_REG), TmpReg) in emitLSL_ri()
4106 TII.get(AArch64::SUBREG_TO_REG), TmpReg) in emitLSR_ri()
4215 TII.get(AArch64::SUBREG_TO_REG), TmpReg) in emitASR_ri()
4274 TII.get(AArch64::SUBREG_TO_REG), Src64) in emitIntExt()
4371 TII.get(AArch64::SUBREG_TO_REG), Reg64) in optimizeIntExtLoad()
4414 TII.get(AArch64::SUBREG_TO_REG), ResultReg) in selectIntExt()
/external/llvm/lib/Target/X86/
DX86InstrExtension.td162 // 64-bit zero-extension patterns use SUBREG_TO_REG and an operation writing a
165 (SUBREG_TO_REG (i64 0), (MOVZX32rr8 GR8:$src), sub_32bit)>;
167 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>;
170 (SUBREG_TO_REG (i64 0), (MOVZX32rr16 GR16:$src), sub_32bit)>;
172 (SUBREG_TO_REG (i64 0), (MOVZX32rm16 addr:$src), sub_32bit)>;
175 // SUBREG_TO_REG to utilize implicit zero-extension, however this isn't possible
180 (SUBREG_TO_REG (i64 0), (MOV32rr GR32:$src), sub_32bit)>;
182 (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src), sub_32bit)>;
DX86InstrCompiler.td258 def : Pat<(i64 0), (SUBREG_TO_REG (i64 0), (MOV32r0), sub_32bit)> {
263 // use MOV32ri with a SUBREG_TO_REG to represent the zero-extension, however
277 (SUBREG_TO_REG (i64 0), (MOV32ri64 mov64imm32:$src), sub_32bit)>;
1067 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>;
1084 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>;
1086 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>;
1088 (SUBREG_TO_REG (i64 0), (MOVZX32rm16 addr:$src), sub_32bit)>;
1090 (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src), sub_32bit)>;
1103 (SUBREG_TO_REG (i64 0), (MOVZX32rr8 GR8 :$src), sub_32bit)>;
1105 (SUBREG_TO_REG (i64 0), (MOVZX32rr16 GR16 :$src), sub_32bit)>;
[all …]
DX86InstrAVX512.td1204 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1205 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1211 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1212 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1377 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1378 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1382 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1383 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1596 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1597 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
[all …]
DX86InstrSSE.td510 def : Pat<(v32i8 immAllZerosV), (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
512 (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
514 def : Pat<(v16i16 immAllZerosV), (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
516 (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
518 def : Pat<(v8i32 immAllZerosV), (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
520 (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
522 def : Pat<(v4i64 immAllZerosV), (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
524 (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
623 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
632 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
[all …]
DX86ISelDAGToDAG.cpp1451 TargetOpcode::SUBREG_TO_REG, DL, MVT::i64, in SelectLEA64_32Addr()
1465 TargetOpcode::SUBREG_TO_REG, DL, MVT::i64, in SelectLEA64_32Addr()
2533 TargetOpcode::SUBREG_TO_REG, dl, MVT::i64, in Select()
2586 TargetOpcode::SUBREG_TO_REG, dl, MVT::i64, in Select()
DX86FastISel.cpp1320 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpcode::SUBREG_TO_REG), in X86SelectZExt()
1693 TII.get(TargetOpcode::SUBREG_TO_REG), TypeEntry.HighInReg) in X86SelectDivRem()
3259 TII.get(TargetOpcode::SUBREG_TO_REG), ResultReg) in X86MaterializeInt()
3287 TII.get(TargetOpcode::SUBREG_TO_REG), ResultReg) in X86MaterializeInt()
/external/llvm/include/llvm/Target/
DTargetOpcodes.h58 SUBREG_TO_REG = 9, enumerator
DTarget.td792 def SUBREG_TO_REG : Instruction {
/external/llvm/lib/Target/Mips/
DMips64r6InstrInfo.td146 (SUBREG_TO_REG (i64 0), (SLTi64 i64:$cond, (Plus1 imm:$imm)),
149 (SUBREG_TO_REG (i64 0), (SLTi64 i64:$cond, (Plus1 imm:$imm)),
155 (SUBREG_TO_REG (i64 0), (SLTiu64 i64:$cond, (Plus1 imm:$imm)),
158 (SUBREG_TO_REG (i64 0), (SLTiu64 i64:$cond, (Plus1 imm:$imm)),
DMipsSEISelDAGToDAG.cpp255 Carry = CurDAG->getMachineNode(Mips::SUBREG_TO_REG, DL, VT, in selectAddESubE()
DMipsSEISelLowering.cpp2959 BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt) in emitINSERT_FW()
2993 BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt) in emitINSERT_FD()
3077 BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt) in emitINSERT_DF_VIDX()
DMips32r6InstrInfo.td477 // We must insert a SUBREG_TO_REG around $fd_in
/external/llvm/lib/Target/PowerPC/
DPPCVSXCopy.cpp108 TII->get(TargetOpcode::SUBREG_TO_REG), NewVReg) in processBlock()
DPPCInstrVSX.td802 (v2f64 (SUBREG_TO_REG (i64 1), $A, sub_64))>;
812 (v2f64 (XXPERMDI (SUBREG_TO_REG (i64 1), $A, sub_64),
813 (SUBREG_TO_REG (i64 1), $A, sub_64), 0))>;
/external/llvm/lib/CodeGen/
DExpandPostRAPseudos.cpp211 case TargetOpcode::SUBREG_TO_REG: in runOnMachineFunction()
DPeepholeOptimizer.cpp389 if (UseMI->getOpcode() == TargetOpcode::SUBREG_TO_REG) in INITIALIZE_PASS_DEPENDENCY()
/external/llvm/lib/Target/Hexagon/
DHexagonMachineScheduler.cpp55 case TargetOpcode::SUBREG_TO_REG: in isResourceAvailable()
107 case TargetOpcode::SUBREG_TO_REG: in reserveResources()
/external/llvm/lib/CodeGen/SelectionDAG/
DResourcePriorityQueue.cpp265 case TargetOpcode::SUBREG_TO_REG: in isResourceAvailable()
305 case TargetOpcode::SUBREG_TO_REG: in reserveResources()
DInstrEmitter.cpp526 Opc == TargetOpcode::SUBREG_TO_REG) { in EmitSubregNode()
559 if (Opc == TargetOpcode::SUBREG_TO_REG) { in EmitSubregNode()
726 Opc == TargetOpcode::SUBREG_TO_REG) { in EmitMachineNode()
DScheduleDAGRRList.cpp1899 Opc == TargetOpcode::SUBREG_TO_REG || in getNodePriority()
2120 Opc == TargetOpcode::SUBREG_TO_REG || in unscheduledNode()
2149 POpc == TargetOpcode::SUBREG_TO_REG) { in unscheduledNode()
2591 Opc == TargetOpcode::SUBREG_TO_REG || in canEnableCoalescing()
2964 SuccOpc == TargetOpcode::SUBREG_TO_REG) in AddPseudoTwoAddrDeps()
/external/llvm/include/llvm/CodeGen/
DMachineInstr.h770 return getOpcode() == TargetOpcode::SUBREG_TO_REG;
811 case TargetOpcode::SUBREG_TO_REG:
/external/llvm/lib/Target/MSP430/
DMSP430InstrInfo.td304 // we can use a SUBREG_TO_REG.
306 (SUBREG_TO_REG (i16 0), GR8:$src, subreg_8bit)>;
1131 (SUBREG_TO_REG (i16 0), GR8:$src, subreg_8bit)>;

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