| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AddressingModes.h | 46 SXTH, enumerator
65 case AArch64_AM::SXTH: return "sxth"; in getShiftExtendName()
132 case 5: return AArch64_AM::SXTH; in getExtendType()
159 case AArch64_AM::SXTH: return 5; break; in getExtendEncoding()
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| D | thumb1.txt | 503 # SXTB/SXTH
|
| D | thumb2.txt | 2193 # SXTH
2247 # SXTH
|
| D | basic-arm-instructions.txt | 2121 # SXTH
|
| /external/v8/test/cctest/ |
| D | test-disasm-arm64.cc | 144 COMPARE(Mov(w14, Operand(w15, SXTH, 2)), "sbfiz w14, w15, #2, #16"); in TEST_()
384 COMPARE(adds(w21, w22, Operand(w23, SXTH, 2)), "adds w21, w22, w23, sxth #2"); in TEST_()
388 COMPARE(cmn(x2, Operand(x3, SXTH, 4)), "cmn x2, w3, sxth #4"); in TEST_()
410 COMPARE(subs(w21, w22, Operand(w23, SXTH, 2)), "subs w21, w22, w23, sxth #2"); in TEST_()
|
| D | test-assembler-arm64.cc | 308 __ Mvn(x13, Operand(x2, SXTH, 3)); in TEST()
381 __ Mov(x26, Operand(x13, SXTH, 3)); in TEST()
567 __ Orr(x11, x0, Operand(x1, SXTH, 1)); in TEST()
664 __ Orn(x11, x0, Operand(x1, SXTH, 1)); in TEST()
733 __ And(x11, x0, Operand(x1, SXTH, 1)); in TEST()
874 __ Bic(x11, x0, Operand(x1, SXTH, 1)); in TEST()
1002 __ Eor(x11, x0, Operand(x1, SXTH, 1)); in TEST()
1071 __ Eon(x11, x0, Operand(x1, SXTH, 1)); in TEST()
3655 __ Add(x16, x0, Operand(x1, SXTH, 2)); in TEST()
3659 __ Add(x20, x0, Operand(x2, SXTH, 2)); in TEST()
[all …]
|
| /external/llvm/test/MC/ARM/ |
| D | basic-thumb-instructions.s | 638 @ SXTB/SXTH
|
| D | basic-thumb2-instructions.s | 3093 @ SXTH
3149 @ SXTH
|
| /external/llvm/lib/Target/AArch64/Utils/ |
| D | AArch64BaseInfo.h | 479 SXTH, enumerator
|
| /external/v8/src/arm64/ |
| D | constants-arm64.h | 347 SXTH = 5, enumerator
|
| D | assembler-arm64.cc | 2404 case SXTH: in EmitExtendShift()
|
| D | simulator-arm64.cc | 935 case SXTH: in ExtendValue()
|
| /external/pcre/dist/sljit/ |
| D | sljitNativeARM_T2_32.c | 161 #define SXTH 0xb200 macro
713 return push_inst16(compiler, SXTH | RD3(dst) | RN3(arg2)); in emit_op_imm()
|
| D | sljitNativeARM_32.c | 122 #define SXTH 0xe6bf0070 macro
1046 return push_inst(compiler, (op == SLJIT_MOV_UH ? UXTH : SXTH) | RD(dst) | RM(src2)); in emit_single_op()
|
| /external/vixl/test/ |
| D | test-assembler-a64.cc | 301 __ Mvn(x13, Operand(x2, SXTH, 3)); in TEST()
474 __ Mov(x26, Operand(x13, SXTH, 3)); in TEST()
561 __ Orr(x11, x0, Operand(x1, SXTH, 1)); in TEST()
655 __ Orn(x11, x0, Operand(x1, SXTH, 1)); in TEST()
722 __ And(x11, x0, Operand(x1, SXTH, 1)); in TEST()
860 __ Bic(x11, x0, Operand(x1, SXTH, 1)); in TEST()
984 __ Eor(x11, x0, Operand(x1, SXTH, 1)); in TEST()
1051 __ Eon(x11, x0, Operand(x1, SXTH, 1)); in TEST()
7461 __ Add(x16, x0, Operand(x1, SXTH, 2)); in TEST()
7465 __ Add(x20, x0, Operand(x2, SXTH, 2)); in TEST()
[all …]
|
| D | test-disasm-a64.cc | 150 COMPARE(Mov(w14, Operand(w15, SXTH, 2)), "sbfiz w14, w15, #2, #16"); in TEST()
384 COMPARE(adds(w21, w22, Operand(w23, SXTH, 2)), "adds w21, w22, w23, sxth #2"); in TEST()
388 COMPARE(cmn(x2, Operand(x3, SXTH, 4)), "cmn x2, w3, sxth #4"); in TEST()
410 COMPARE(subs(w21, w22, Operand(w23, SXTH, 2)), "subs w21, w22, w23, sxth #2"); in TEST()
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMFastISel.cpp | 2651 /* 16 bit sext */ { { ARM::SXTH , 0, ARM_AM::no_shift, 0 }, in ARMEmitIntExt()
2891 { { ARM::SXTH, ARM::t2SXTH }, 0, 0, MVT::i16 },
|
| D | ARMScheduleSwift.td | 1194 (instregex "SXTB", "SXTH", "SXTB16", "UXTB", "UXTH", "UXTB16",
|
| D | ARMInstrInfo.td | 3322 def SXTH : AI_ext_rrot<0b01101011,
5423 def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>;
5529 (SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
|
| /external/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 938 ET == AArch64_AM::UXTH || ET == AArch64_AM::SXTH || in isExtend()
2274 .Case("sxth", AArch64_AM::SXTH) in tryParseOptionalShiftExtend()
|
| /external/vixl/src/vixl/a64/ |
| D | constants-a64.h | 281 SXTH = 5, enumerator
|
| D | simulator-a64.cc | 384 case SXTH: in ExtendValue()
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelDAGToDAG.cpp | 359 return AArch64_AM::SXTH; in getExtendTypeForNode()
|
| D | AArch64FastISel.cpp | 1101 ExtendType = IsZExt ? AArch64_AM::UXTH : AArch64_AM::SXTH; in emitAddSub()
|
| /external/vixl/doc/ |
| D | supported-instructions.md | 1257 ### SXTH ### subsection
|