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Searched refs:SrcVT (Results 1 – 25 of 34) sorted by relevance

12

/external/llvm/lib/Target/Mips/
DMipsFastISel.cpp120 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
121 bool emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg,
124 bool emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
126 bool emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
127 bool emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
129 bool emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
854 EVT SrcVT = TLI.getValueType(Src->getType(), true); in selectFPExt() local
857 if (SrcVT != MVT::f32 || DestVT != MVT::f64) in selectFPExt()
877 EVT SrcVT = TLI.getValueType(Src->getType(), true); in selectFPTrunc() local
880 if (SrcVT != MVT::f64 || DestVT != MVT::f32) in selectFPTrunc()
[all …]
DMipsMSAInstrInfo.td3577 class MSABitconvertPat<ValueType DstVT, ValueType SrcVT,
3579 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3580 (COPY_TO_REGCLASS SrcVT:$src, DstRC), preds>;
3634 class MSABitconvertReverseQuartersPat<ValueType DstVT, ValueType SrcVT,
3637 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3638 (COPY_TO_REGCLASS (Insn (COPY_TO_REGCLASS SrcVT:$src, ViaRC), 27),
3642 class MSABitconvertReverseHalvesPat<ValueType DstVT, ValueType SrcVT,
3645 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3646 (COPY_TO_REGCLASS (Insn (COPY_TO_REGCLASS SrcVT:$src, ViaRC), 177),
3650 class MSABitconvertReverseBInHPat<ValueType DstVT, ValueType SrcVT,
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/external/llvm/lib/Target/PowerPC/
DPPCFastISel.cpp159 bool PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
783 MVT SrcVT = SrcEVT.getSimpleVT(); in PPCEmitCmp() local
785 if (SrcVT == MVT::i1 && PPCSubTarget->useCRBits()) in PPCEmitCmp()
798 if (SrcVT == MVT::i64 || SrcVT == MVT::i32 || SrcVT == MVT::i16 || in PPCEmitCmp()
799 SrcVT == MVT::i8 || SrcVT == MVT::i1) { in PPCEmitCmp()
809 switch (SrcVT.SimpleTy) { in PPCEmitCmp()
849 if (!PPCEmitIntExt(SrcVT, SrcReg1, MVT::i32, ExtReg, IsZExt)) in PPCEmitCmp()
855 if (!PPCEmitIntExt(SrcVT, SrcReg2, MVT::i32, ExtReg, IsZExt)) in PPCEmitCmp()
874 EVT SrcVT = TLI.getValueType(Src->getType(), true); in SelectFPExt() local
877 if (SrcVT != MVT::f32 || DestVT != MVT::f64) in SelectFPExt()
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/external/llvm/lib/Target/AArch64/
DAArch64FastISel.cpp153 bool optimizeIntExtLoad(const Instruction *I, MVT RetVT, MVT SrcVT);
188 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
219 unsigned emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
223 unsigned emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
227 unsigned emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
1107 MVT SrcVT = RetVT; in emitAddSub() local
1134 LHSReg = emitIntExt(SrcVT, LHSReg, RetVT, IsZExt); in emitAddSub()
1225 RHSReg = emitIntExt(SrcVT, RHSReg, RetVT, IsZExt); in emitAddSub()
2320 MVT SrcVT; in selectBranch() local
2322 isTypeSupported(TI->getOperand(0)->getType(), SrcVT)) { in selectBranch()
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DAArch64ISelDAGToDAG.cpp350 EVT SrcVT; in getExtendTypeForNode() local
352 SrcVT = cast<VTSDNode>(N.getOperand(1))->getVT(); in getExtendTypeForNode()
354 SrcVT = N.getOperand(0).getValueType(); in getExtendTypeForNode()
356 if (!IsLoadStore && SrcVT == MVT::i8) in getExtendTypeForNode()
358 else if (!IsLoadStore && SrcVT == MVT::i16) in getExtendTypeForNode()
360 else if (SrcVT == MVT::i32) in getExtendTypeForNode()
362 assert(SrcVT != MVT::i64 && "extend from 64-bits?"); in getExtendTypeForNode()
367 EVT SrcVT = N.getOperand(0).getValueType(); in getExtendTypeForNode() local
368 if (!IsLoadStore && SrcVT == MVT::i8) in getExtendTypeForNode()
370 else if (!IsLoadStore && SrcVT == MVT::i16) in getExtendTypeForNode()
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DAArch64ISelLowering.cpp3367 EVT SrcVT = In2.getValueType(); in LowerFCOPYSIGN() local
3368 if (SrcVT != VT) { in LowerFCOPYSIGN()
3369 if (SrcVT == MVT::f32 && VT == MVT::f64) in LowerFCOPYSIGN()
3371 else if (SrcVT == MVT::f64 && VT == MVT::f32) in LowerFCOPYSIGN()
4603 EVT SrcVT = Src.ShuffleVec.getValueType(); in ReconstructShuffle() local
4605 if (SrcVT.getSizeInBits() == VT.getSizeInBits()) in ReconstructShuffle()
4610 EVT EltVT = SrcVT.getVectorElementType(); in ReconstructShuffle()
4614 if (SrcVT.getSizeInBits() < VT.getSizeInBits()) { in ReconstructShuffle()
4615 assert(2 * SrcVT.getSizeInBits() == VT.getSizeInBits()); in ReconstructShuffle()
4624 assert(SrcVT.getSizeInBits() == 2 * VT.getSizeInBits()); in ReconstructShuffle()
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/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeVectorOps.cpp482 EVT SrcVT = LD->getMemoryVT(); in ExpandLoad() local
487 unsigned NumElem = SrcVT.getVectorNumElements(); in ExpandLoad()
489 EVT SrcEltVT = SrcVT.getScalarType(); in ExpandLoad()
492 if (SrcVT.getVectorNumElements() > 1 && !SrcEltVT.isByteSized()) { in ExpandLoad()
508 unsigned RemainingBytes = SrcVT.getStoreSize(); in ExpandLoad()
596 unsigned Stride = SrcVT.getScalarType().getSizeInBits()/8; in ExpandLoad()
602 SrcVT.getScalarType(), in ExpandLoad()
787 EVT SrcVT = Src.getValueType(); in ExpandANY_EXTEND_VECTOR_INREG() local
788 int NumSrcElements = SrcVT.getVectorNumElements(); in ExpandANY_EXTEND_VECTOR_INREG()
802 DAG.getVectorShuffle(SrcVT, DL, Src, DAG.getUNDEF(SrcVT), ShuffleMask)); in ExpandANY_EXTEND_VECTOR_INREG()
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DFastISel.cpp1227 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); in selectCast() local
1230 if (SrcVT == MVT::Other || !SrcVT.isSimple() || DstVT == MVT::Other || in selectCast()
1240 if (!TLI.isTypeLegal(SrcVT)) in selectCast()
1250 unsigned ResultReg = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), in selectCast()
1277 MVT SrcVT = SrcEVT.getSimpleVT(); in selectBitCast() local
1286 if (SrcVT == DstVT) { in selectBitCast()
1287 const TargetRegisterClass *SrcClass = TLI.getRegClassFor(SrcVT); in selectBitCast()
1299 ResultReg = fastEmit_r(SrcVT, DstVT, ISD::BITCAST, Op0, Op0IsKill); in selectBitCast()
1564 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); in selectOperator() local
1566 if (DstVT.bitsGT(SrcVT)) in selectOperator()
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DLegalizeDAG.cpp930 EVT SrcVT = LD->getMemoryVT(); in LegalizeLoadOps() local
931 unsigned SrcWidth = SrcVT.getSizeInBits(); in LegalizeLoadOps()
938 if (SrcWidth != SrcVT.getStoreSizeInBits() && in LegalizeLoadOps()
946 (SrcVT != MVT::i1 || in LegalizeLoadOps()
951 unsigned NewWidth = SrcVT.getStoreSizeInBits(); in LegalizeLoadOps()
973 Result, DAG.getValueType(SrcVT)); in LegalizeLoadOps()
978 DAG.getValueType(SrcVT)); in LegalizeLoadOps()
984 assert(!SrcVT.isVector() && "Unsupported extload!"); in LegalizeLoadOps()
1061 SrcVT.getSimpleVT())) { in LegalizeLoadOps()
1093 if (!TLI.isLoadExtLegal(ISD::EXTLOAD, Node->getValueType(0), SrcVT)) { in LegalizeLoadOps()
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DLegalizeFloatTypes.cpp1278 EVT SrcVT = Src.getValueType(); in ExpandFloatRes_XINT_TO_FP() local
1285 if (SrcVT.bitsLE(MVT::i32)) { in ExpandFloatRes_XINT_TO_FP()
1294 if (SrcVT.bitsLE(MVT::i64)) { in ExpandFloatRes_XINT_TO_FP()
1298 } else if (SrcVT.bitsLE(MVT::i128)) { in ExpandFloatRes_XINT_TO_FP()
1313 SrcVT = Src.getValueType(); in ExpandFloatRes_XINT_TO_FP()
1321 switch (SrcVT.getSimpleVT().SimpleTy) { in ExpandFloatRes_XINT_TO_FP()
1339 Lo = DAG.getSelectCC(dl, Src, DAG.getConstant(0, SrcVT), in ExpandFloatRes_XINT_TO_FP()
DLegalizeIntegerTypes.cpp2838 EVT SrcVT = Op.getValueType(); in ExpandIntOp_UINT_TO_FP() local
2846 if (APFloat::semanticsPrecision(sem) >= SrcVT.getSizeInBits()-1 && in ExpandIntOp_UINT_TO_FP()
2847 TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){ in ExpandIntOp_UINT_TO_FP()
2861 if (SrcVT == MVT::i32) in ExpandIntOp_UINT_TO_FP()
2863 else if (SrcVT == MVT::i64) in ExpandIntOp_UINT_TO_FP()
2865 else if (SrcVT == MVT::i128) in ExpandIntOp_UINT_TO_FP()
2905 RTLIB::Libcall LC = RTLIB::getUINTTOFP(SrcVT, DstVT); in ExpandIntOp_UINT_TO_FP()
DLegalizeVectorTypes.cpp1104 EVT SrcVT = N->getOperand(0).getValueType(); in SplitVecRes_ExtendOp() local
1122 unsigned NumElements = SrcVT.getVectorNumElements(); in SplitVecRes_ExtendOp()
1124 SrcVT.getSizeInBits() * 2 < DestVT.getSizeInBits()) { in SplitVecRes_ExtendOp()
1128 Ctx, SrcVT.getVectorElementType().getSizeInBits() * 2), in SplitVecRes_ExtendOp()
1131 EVT::getVectorVT(Ctx, SrcVT.getVectorElementType(), NumElements / 2); in SplitVecRes_ExtendOp()
1134 if (TLI.isTypeLegal(SrcVT) && !TLI.isTypeLegal(SplitSrcVT) && in SplitVecRes_ExtendOp()
/external/llvm/lib/Target/X86/InstPrinter/
DX86InstComments.cpp28 static void getZeroExtensionTypes(const MCInst *MI, MVT &SrcVT, MVT &DstVT) { in getZeroExtensionTypes() argument
37 SrcVT = MVT::v16i8; in getZeroExtensionTypes()
42 SrcVT = MVT::v16i8; in getZeroExtensionTypes()
49 SrcVT = MVT::v16i8; in getZeroExtensionTypes()
54 SrcVT = MVT::v16i8; in getZeroExtensionTypes()
61 SrcVT = MVT::v16i8; in getZeroExtensionTypes()
66 SrcVT = MVT::v16i8; in getZeroExtensionTypes()
74 SrcVT = MVT::v8i16; in getZeroExtensionTypes()
79 SrcVT = MVT::v8i16; in getZeroExtensionTypes()
86 SrcVT = MVT::v8i16; in getZeroExtensionTypes()
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/external/llvm/lib/Target/ARM/
DARMFastISel.cpp183 unsigned ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
1370 MVT SrcVT = SrcEVT.getSimpleVT(); in ARMEmitCmp() local
1384 if (SrcVT == MVT::i32 || SrcVT == MVT::i16 || SrcVT == MVT::i8 || in ARMEmitCmp()
1385 SrcVT == MVT::i1) { in ARMEmitCmp()
1399 if (SrcVT == MVT::f32 || SrcVT == MVT::f64) in ARMEmitCmp()
1407 switch (SrcVT.SimpleTy) { in ARMEmitCmp()
1449 SrcReg1 = ARMEmitIntExt(SrcVT, SrcReg1, MVT::i32, isZExt); in ARMEmitCmp()
1452 SrcReg2 = ARMEmitIntExt(SrcVT, SrcReg2, MVT::i32, isZExt); in ARMEmitCmp()
1563 MVT SrcVT = SrcEVT.getSimpleVT(); in SelectIToFP() local
1564 if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8) in SelectIToFP()
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/external/llvm/lib/Target/X86/
DX86SelectionDAGInfo.cpp278 EVT SrcVT = Src.getValueType(); in EmitTargetCodeForMemcpy() local
283 DAG.getNode(ISD::ADD, dl, SrcVT, Src, in EmitTargetCodeForMemcpy()
284 DAG.getConstant(Offset, SrcVT)), in EmitTargetCodeForMemcpy()
DX86FastISel.cpp95 bool X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT,
523 unsigned Src, EVT SrcVT, in X86FastEmitExtend() argument
525 unsigned RR = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc, in X86FastEmitExtend()
1016 EVT SrcVT = TLI.getValueType(RV->getType()); in X86SelectRet() local
1019 if (SrcVT != DstVT) { in X86SelectRet()
1020 if (SrcVT != MVT::i1 && SrcVT != MVT::i8 && SrcVT != MVT::i16) in X86SelectRet()
1028 if (SrcVT == MVT::i1) { in X86SelectRet()
1032 SrcVT = MVT::i8; in X86SelectRet()
1036 SrcReg = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Op, in X86SelectRet()
1294 MVT SrcVT = TLI.getSimpleValueType(I->getOperand(0)->getType()); in X86SelectZExt() local
[all …]
DX86ISelLowering.cpp4439 EVT SrcVT = V.getValueType(); in getShuffleScalarElt() local
4442 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems) in getShuffleScalarElt()
11394 MVT SrcVT = Op.getOperand(0).getSimpleValueType(); in LowerSINT_TO_FP() local
11397 if (SrcVT.isVector()) { in LowerSINT_TO_FP()
11398 if (SrcVT.getVectorElementType() == MVT::i1) { in LowerSINT_TO_FP()
11399 MVT IntegerVT = MVT::getVectorVT(MVT::i32, SrcVT.getVectorNumElements()); in LowerSINT_TO_FP()
11407 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 && in LowerSINT_TO_FP()
11412 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType())) in LowerSINT_TO_FP()
11414 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) && in LowerSINT_TO_FP()
11419 unsigned Size = SrcVT.getSizeInBits()/8; in LowerSINT_TO_FP()
[all …]
DX86ISelLowering.h848 SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot,
DX86ISelDAGToDAG.cpp505 MVT SrcVT = N->getOperand(0).getSimpleValueType(); in PreprocessISelDAG() local
509 if (SrcVT.isVector() || DstVT.isVector()) in PreprocessISelDAG()
516 bool SrcIsSSE = X86Lowering->isScalarFPTypeInSSEReg(SrcVT); in PreprocessISelDAG()
537 MemVT = SrcIsSSE ? SrcVT : DstVT; in PreprocessISelDAG()
/external/llvm/lib/Target/X86/Utils/
DX86ShuffleDecode.cpp402 void DecodeZeroExtendMask(MVT SrcVT, MVT DstVT, SmallVectorImpl<int> &Mask) { in DecodeZeroExtendMask() argument
404 unsigned SrcScalarBits = SrcVT.getScalarSizeInBits(); in DecodeZeroExtendMask()
409 assert(SrcVT.getVectorNumElements() >= NumDstElts && in DecodeZeroExtendMask()
DX86ShuffleDecode.h94 void DecodeZeroExtendMask(MVT SrcVT, MVT DstVT,
/external/llvm/lib/Transforms/Scalar/
DScalarizer.cpp483 VectorType *SrcVT = dyn_cast<VectorType>(BCI.getSrcTy()); in visitBitCastInst() local
484 if (!DstVT || !SrcVT) in visitBitCastInst()
488 unsigned SrcNumElems = SrcVT->getNumElements(); in visitBitCastInst()
520 Type *MidTy = VectorType::get(SrcVT->getElementType(), FanIn); in visitBitCastInst()
/external/llvm/lib/Target/R600/
DSIISelLowering.cpp1257 EVT SrcVT = Src.getValueType(); in performUCharToFloatCombine() local
1263 if (DCI.isAfterLegalizeVectorOps() && SrcVT == MVT::i32) { in performUCharToFloatCombine()
1276 !SrcVT.isVector() || in performUCharToFloatCombine()
1277 SrcVT.getVectorElementType() != MVT::i8) { in performUCharToFloatCombine()
1285 unsigned NElts = SrcVT.getVectorNumElements(); in performUCharToFloatCombine()
1286 if (!SrcVT.isSimple() && NElts != 3) in performUCharToFloatCombine()
1292 EVT LoadVT = getEquivalentMemType(*DAG.getContext(), SrcVT); in performUCharToFloatCombine()
1293 EVT RegVT = getEquivalentLoadRegType(*DAG.getContext(), SrcVT); in performUCharToFloatCombine()
DAMDGPUISelDAGToDAG.cpp1116 EVT SrcVT = Src.getValueType(); in SelectAddrSpaceCast() local
1118 unsigned SrcSize = SrcVT.getSizeInBits(); in SelectAddrSpaceCast()
/external/llvm/lib/CodeGen/
DCodeGenPrepare.cpp722 EVT SrcVT = TLI.getValueType(CI->getOperand(0)->getType()); in OptimizeNoopCopyExpression() local
726 if (SrcVT.isInteger() != DstVT.isInteger()) in OptimizeNoopCopyExpression()
731 if (SrcVT.bitsLT(DstVT)) return false; in OptimizeNoopCopyExpression()
736 if (TLI.getTypeAction(CI->getContext(), SrcVT) == in OptimizeNoopCopyExpression()
738 SrcVT = TLI.getTypeToTransformTo(CI->getContext(), SrcVT); in OptimizeNoopCopyExpression()
744 if (SrcVT != DstVT) in OptimizeNoopCopyExpression()

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