| /external/llvm/lib/CodeGen/ |
| D | LiveVariables.cpp | 198 unsigned SubReg = *SubRegs; in FindLastPartialDef() local
199 MachineInstr *Def = PhysRegDef[SubReg]; in FindLastPartialDef()
204 LastDefReg = SubReg; in FindLastPartialDef()
252 unsigned SubReg = *SubRegs; in HandlePhysRegUse() local
253 if (Processed.count(SubReg)) in HandlePhysRegUse()
255 if (PartDefRegs.count(SubReg)) in HandlePhysRegUse()
259 LastPartialDef->addOperand(MachineOperand::CreateReg(SubReg, in HandlePhysRegUse()
262 PhysRegDef[SubReg] = LastPartialDef; in HandlePhysRegUse()
263 for (MCSubRegIterator SS(SubReg, TRI); SS.isValid(); ++SS) in HandlePhysRegUse()
291 unsigned SubReg = *SubRegs; in FindLastRefOrPartRef() local
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| D | LiveRangeCalc.cpp | 65 unsigned SubReg = MO.getSubReg(); in calculate() local
66 if (LI.hasSubRanges() || (SubReg != 0 && TrackSubRegs)) { in calculate()
67 unsigned Mask = SubReg != 0 ? TRI.getSubRegIndexLaneMask(SubReg) in calculate()
158 unsigned SubReg = MO.getSubReg(); in extendToUses() local
159 if (SubReg != 0) { in extendToUses()
160 unsigned SubRegMask = TRI.getSubRegIndexLaneMask(SubReg); in extendToUses()
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| D | PeepholeOptimizer.cpp | 144 bool findNextSource(unsigned &Reg, unsigned &SubReg);
544 bool PeepholeOptimizer::findNextSource(unsigned &Reg, unsigned &SubReg) { in findNextSource() argument
553 unsigned DefSubReg = SubReg; in findNextSource()
589 SubReg = SrcSubReg; in findNextSource()
956 if (!findNextSource(Src.Reg, Src.SubReg)) in optimizeUncoalescableCopy()
971 NewVR).addReg(Src.Reg, 0, Src.SubReg); in optimizeUncoalescableCopy()
972 NewCopy->getOperand(0).setSubReg(Def.SubReg); in optimizeUncoalescableCopy()
973 if (Def.SubReg) in optimizeUncoalescableCopy()
1281 if (RegSeqInput.SubReg) in getNextSourceFromRegSequence()
1286 SrcSubReg = RegSeqInput.SubReg; in getNextSourceFromRegSequence()
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| D | MachineInstrBundle.cpp | 176 unsigned SubReg = *SubRegs; in finalizeBundle() local
177 if (LocalDefSet.insert(SubReg).second) in finalizeBundle()
178 LocalDefs.push_back(SubReg); in finalizeBundle()
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| D | LiveIntervalAnalysis.cpp | 513 unsigned SubReg = MO.getSubReg(); in shrinkToUses() local
514 if (SubReg != 0) { in shrinkToUses()
515 unsigned SubRegMask = TRI->getSubRegIndexLaneMask(SubReg); in shrinkToUses()
946 unsigned SubReg = MO->getSubReg(); in updateAllRanges() local
947 unsigned LaneMask = TRI.getSubRegIndexLaneMask(SubReg); in updateAllRanges()
1183 unsigned SubReg = MO.getSubReg(); in findLastUseBefore() local
1184 if (SubReg != 0 && LaneMask != 0 in findLastUseBefore()
1185 && (TRI.getSubRegIndexLaneMask(SubReg) & LaneMask) == 0) in findLastUseBefore()
1284 unsigned SubReg = MO.getSubReg(); in repairOldRegInRange() local
1285 unsigned Mask = TRI->getSubRegIndexLaneMask(SubReg); in repairOldRegInRange()
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| D | VirtRegMap.cpp | 261 unsigned SubReg = SR.getSubReg(); in addMBBLiveIns() local
267 if (!LiveIn[i]->isLiveIn(SubReg)) in addMBBLiveIns()
268 LiveIn[i]->addLiveIn(SubReg); in addMBBLiveIns()
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| D | TargetInstrInfo.cpp | 919 InputReg.SubReg = MOReg.getSubReg(); in getExtractSubregInputs()
942 BaseReg.SubReg = MOBaseReg.getSubReg(); in getInsertSubregInputs()
945 InsertedReg.SubReg = MOInsertedReg.getSubReg(); in getInsertSubregInputs()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64AdvSIMDScalarPass.cpp | 101 static bool isGPR64(unsigned Reg, unsigned SubReg, in isGPR64() argument
103 if (SubReg) in isGPR64()
110 static bool isFPR64(unsigned Reg, unsigned SubReg, in isFPR64() argument
114 SubReg == 0) || in isFPR64()
116 SubReg == AArch64::dsub); in isFPR64()
118 return (AArch64::FPR64RegClass.contains(Reg) && SubReg == 0) || in isFPR64()
119 (AArch64::FPR128RegClass.contains(Reg) && SubReg == AArch64::dsub); in isFPR64()
126 unsigned &SubReg) { in getSrcFromCopy() argument
127 SubReg = 0; in getSrcFromCopy()
135 SubReg = AArch64::dsub; in getSrcFromCopy()
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| D | AArch64ISelDAGToDAG.cpp | 531 SDValue SubReg = CurDAG->getTargetConstant(AArch64::sub_32, MVT::i32); in narrowIfNeeded() local
533 SDLoc(N), MVT::i32, N, SubReg); in narrowIfNeeded()
691 SDValue SubReg = CurDAG->getTargetConstant(AArch64::sub_32, MVT::i32); in Widen() local
696 TargetOpcode::INSERT_SUBREG, SDLoc(N), MVT::i64, ImpDef, N, SubReg); in Widen()
1041 SDValue SubReg = CurDAG->getTargetConstant(AArch64::sub_32, MVT::i32); in SelectIndexedLoad() local
1045 CurDAG->getTargetConstant(0, MVT::i64), LoadedVal, SubReg), in SelectIndexedLoad()
1601 SDValue SubReg = CurDAG->getTargetConstant(AArch64::sub_32, MVT::i32); in SelectBitfieldExtractOp() local
1604 SDValue(BFM, 0), SubReg); in SelectBitfieldExtractOp()
2163 unsigned SubReg; in Select() local
2171 SubReg = AArch64::dsub; in Select()
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| D | AArch64InstrInfo.cpp | 1521 int SubReg = 0, End = NumRegs, Incr = 1; in copyPhysRegTuple() local
1523 SubReg = NumRegs - 1; in copyPhysRegTuple()
1528 for (; SubReg != End; SubReg += Incr) { in copyPhysRegTuple()
1530 AddSubReg(MIB, DestReg, Indices[SubReg], RegState::Define, TRI); in copyPhysRegTuple()
1531 AddSubReg(MIB, SrcReg, Indices[SubReg], 0, TRI); in copyPhysRegTuple()
1532 AddSubReg(MIB, SrcReg, Indices[SubReg], getKillRegState(KillSrc), TRI); in copyPhysRegTuple()
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| /external/llvm/lib/Target/R600/ |
| D | SIFixSGPRCopies.cpp | 91 unsigned SubReg) const;
95 unsigned SubReg) const;
138 unsigned SubReg) const { in inferRegClassFromUses()
145 RC = TRI->getSubRegClass(RC, SubReg); in inferRegClassFromUses()
164 unsigned SubReg) const { in inferRegClassFromDef()
167 return TRI->getSubRegClass(RC, SubReg); in inferRegClassFromDef()
171 return TRI->getSubRegClass(MRI.getRegClass(Reg), SubReg); in inferRegClassFromDef()
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| D | SIRegisterInfo.cpp | 175 unsigned SubReg = NumSubRegs > 1 ? in buildScratchLoadStore() local
181 .addReg(SubReg, getDefRegState(IsLoad)) in buildScratchLoadStore()
216 unsigned SubReg = getPhysRegSubReg(MI->getOperand(0).getReg(), in eliminateFrameIndex() local
229 .addReg(SubReg) in eliminateFrameIndex()
246 unsigned SubReg = getPhysRegSubReg(MI->getOperand(0).getReg(), in eliminateFrameIndex() local
248 bool isM0 = SubReg == AMDGPU::M0; in eliminateFrameIndex()
258 SubReg = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, MI, 0); in eliminateFrameIndex()
262 SubReg) in eliminateFrameIndex()
268 .addReg(SubReg); in eliminateFrameIndex()
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| D | SILowerControlFlow.cpp | 395 unsigned SubReg = TRI->getSubReg(Vec, AMDGPU::sub0); in IndirectSrc() local
396 if (!SubReg) in IndirectSrc()
397 SubReg = Vec; in IndirectSrc()
401 .addReg(SubReg + Off) in IndirectSrc()
416 unsigned SubReg = TRI->getSubReg(Dst, AMDGPU::sub0); in IndirectDst() local
417 if (!SubReg) in IndirectDst()
418 SubReg = Dst; in IndirectDst()
422 .addReg(SubReg + Off, RegState::Define) in IndirectDst()
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| D | R600OptimizeVectorRegisters.cpp | 192 unsigned SubReg = (*It).first; in RebuildVector() local
199 .addReg(SubReg) in RebuildVector()
201 UpdatedRegToChan[SubReg] = Chan; in RebuildVector()
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| D | SIInstrInfo.cpp | 809 unsigned SubReg = Src0.getSubReg(); in commuteInstruction() local
816 Src1.setSubReg(SubReg); in commuteInstruction()
1502 unsigned SubReg = MRI.createVirtualRegister(SubRC); in buildExtractSubReg() local
1514 BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), SubReg) in buildExtractSubReg()
1517 return SubReg; in buildExtractSubReg()
1537 unsigned SubReg = buildExtractSubReg(MII, MRI, Op, SuperRC, in buildExtractSubRegOrImm() local
1539 return MachineOperand::CreateReg(SubReg, false); in buildExtractSubRegOrImm()
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| /external/llvm/lib/MC/ |
| D | MCRegisterInfo.cpp | 38 unsigned MCRegisterInfo::getSubRegIndex(unsigned Reg, unsigned SubReg) const { in getSubRegIndex()
39 assert(SubReg && SubReg < getNumRegs() && "This is not a register"); in getSubRegIndex()
44 if (*Subs == SubReg) in getSubRegIndex()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCRegisterInfo.td | 36 class GP8<GPR SubReg, string n> : PPCReg<n> {
37 let HWEncoding = SubReg.HWEncoding;
38 let SubRegs = [SubReg];
53 class QFPR<FPR SubReg, string n> : PPCReg<n> {
54 let HWEncoding = SubReg.HWEncoding;
55 let SubRegs = [SubReg];
67 class VR<VF SubReg, string n> : PPCReg<n> {
68 let HWEncoding{4-0} = SubReg.HWEncoding{4-0};
70 let SubRegs = [SubReg];
76 class VSRL<FPR SubReg, string n> : PPCReg<n> {
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| /external/llvm/include/llvm/Target/ |
| D | TargetRegisterInfo.h | 843 unsigned SubReg, in shouldCoalesce() argument
876 unsigned SubReg; variable
887 SubReg(0),
898 unsigned getSubReg() const { return SubReg; } in getSubReg()
908 SubReg = *Idx++;
909 if (!SubReg)
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| D | TargetInstrInfo.h | 277 unsigned SubReg; member
278 RegSubRegPair(unsigned Reg = 0, unsigned SubReg = 0)
279 : Reg(Reg), SubReg(SubReg) {} in Reg()
286 RegSubRegPairAndIdx(unsigned Reg = 0, unsigned SubReg = 0,
288 : RegSubRegPair(Reg, SubReg), SubIdx(SubIdx) {} in RegSubRegPair()
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZElimCompare.cpp | 109 static bool resultTests(MachineInstr *MI, unsigned Reg, unsigned SubReg) { in resultTests() argument
114 MI->getOperand(0).getSubReg() == SubReg) in resultTests()
131 MI->getOperand(1).getSubReg() == SubReg) in resultTests()
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| D | SystemZISelLowering.h | 350 bool ClearEven, unsigned SubReg) const;
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| /external/llvm/lib/Target/ARM/ |
| D | ARMBaseRegisterInfo.h | 183 unsigned SubReg,
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| /external/llvm/include/llvm/CodeGen/ |
| D | MachineOperand.h | 590 unsigned SubReg = 0,
608 Op.setSubReg(SubReg);
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| D | MachineInstrBuilder.h | 69 unsigned SubReg = 0) const {
79 SubReg,
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 522 unsigned SubReg = getRegisterInfo().getSubReg(SrcReg, SubIdx); in expandExtractElementF64() local
548 BuildMI(MBB, I, dl, get(Mips::MFC1), DstReg).addReg(SubReg); in expandExtractElementF64()
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