1 //===-- SystemZISelLowering.h - SystemZ DAG lowering interface --*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the interfaces that SystemZ uses to lower LLVM code into a
11 // selection DAG.
12 //
13 //===----------------------------------------------------------------------===//
14
15 #ifndef LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZISELLOWERING_H
16 #define LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZISELLOWERING_H
17
18 #include "SystemZ.h"
19 #include "llvm/CodeGen/MachineBasicBlock.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/Target/TargetLowering.h"
22
23 namespace llvm {
24 namespace SystemZISD {
25 enum {
26 FIRST_NUMBER = ISD::BUILTIN_OP_END,
27
28 // Return with a flag operand. Operand 0 is the chain operand.
29 RET_FLAG,
30
31 // Calls a function. Operand 0 is the chain operand and operand 1
32 // is the target address. The arguments start at operand 2.
33 // There is an optional glue operand at the end.
34 CALL,
35 SIBCALL,
36
37 // TLS calls. Like regular calls, except operand 1 is the TLS symbol.
38 // (The call target is implicitly __tls_get_offset.)
39 TLS_GDCALL,
40 TLS_LDCALL,
41
42 // Wraps a TargetGlobalAddress that should be loaded using PC-relative
43 // accesses (LARL). Operand 0 is the address.
44 PCREL_WRAPPER,
45
46 // Used in cases where an offset is applied to a TargetGlobalAddress.
47 // Operand 0 is the full TargetGlobalAddress and operand 1 is a
48 // PCREL_WRAPPER for an anchor point. This is used so that we can
49 // cheaply refer to either the full address or the anchor point
50 // as a register base.
51 PCREL_OFFSET,
52
53 // Integer absolute.
54 IABS,
55
56 // Integer comparisons. There are three operands: the two values
57 // to compare, and an integer of type SystemZICMP.
58 ICMP,
59
60 // Floating-point comparisons. The two operands are the values to compare.
61 FCMP,
62
63 // Test under mask. The first operand is ANDed with the second operand
64 // and the condition codes are set on the result. The third operand is
65 // a boolean that is true if the condition codes need to distinguish
66 // between CCMASK_TM_MIXED_MSB_0 and CCMASK_TM_MIXED_MSB_1 (which the
67 // register forms do but the memory forms don't).
68 TM,
69
70 // Branches if a condition is true. Operand 0 is the chain operand;
71 // operand 1 is the 4-bit condition-code mask, with bit N in
72 // big-endian order meaning "branch if CC=N"; operand 2 is the
73 // target block and operand 3 is the flag operand.
74 BR_CCMASK,
75
76 // Selects between operand 0 and operand 1. Operand 2 is the
77 // mask of condition-code values for which operand 0 should be
78 // chosen over operand 1; it has the same form as BR_CCMASK.
79 // Operand 3 is the flag operand.
80 SELECT_CCMASK,
81
82 // Evaluates to the gap between the stack pointer and the
83 // base of the dynamically-allocatable area.
84 ADJDYNALLOC,
85
86 // Extracts the value of a 32-bit access register. Operand 0 is
87 // the number of the register.
88 EXTRACT_ACCESS,
89
90 // Count number of bits set in operand 0 per byte.
91 POPCNT,
92
93 // Wrappers around the ISD opcodes of the same name. The output and
94 // first input operands are GR128s. The trailing numbers are the
95 // widths of the second operand in bits.
96 UMUL_LOHI64,
97 SDIVREM32,
98 SDIVREM64,
99 UDIVREM32,
100 UDIVREM64,
101
102 // Use a series of MVCs to copy bytes from one memory location to another.
103 // The operands are:
104 // - the target address
105 // - the source address
106 // - the constant length
107 //
108 // This isn't a memory opcode because we'd need to attach two
109 // MachineMemOperands rather than one.
110 MVC,
111
112 // Like MVC, but implemented as a loop that handles X*256 bytes
113 // followed by straight-line code to handle the rest (if any).
114 // The value of X is passed as an additional operand.
115 MVC_LOOP,
116
117 // Similar to MVC and MVC_LOOP, but for logic operations (AND, OR, XOR).
118 NC,
119 NC_LOOP,
120 OC,
121 OC_LOOP,
122 XC,
123 XC_LOOP,
124
125 // Use CLC to compare two blocks of memory, with the same comments
126 // as for MVC and MVC_LOOP.
127 CLC,
128 CLC_LOOP,
129
130 // Use an MVST-based sequence to implement stpcpy().
131 STPCPY,
132
133 // Use a CLST-based sequence to implement strcmp(). The two input operands
134 // are the addresses of the strings to compare.
135 STRCMP,
136
137 // Use an SRST-based sequence to search a block of memory. The first
138 // operand is the end address, the second is the start, and the third
139 // is the character to search for. CC is set to 1 on success and 2
140 // on failure.
141 SEARCH_STRING,
142
143 // Store the CC value in bits 29 and 28 of an integer.
144 IPM,
145
146 // Perform a serialization operation. (BCR 15,0 or BCR 14,0.)
147 SERIALIZE,
148
149 // Transaction begin. The first operand is the chain, the second
150 // the TDB pointer, and the third the immediate control field.
151 // Returns chain and glue.
152 TBEGIN,
153 TBEGIN_NOFLOAT,
154
155 // Transaction end. Just the chain operand. Returns chain and glue.
156 TEND,
157
158 // Wrappers around the inner loop of an 8- or 16-bit ATOMIC_SWAP or
159 // ATOMIC_LOAD_<op>.
160 //
161 // Operand 0: the address of the containing 32-bit-aligned field
162 // Operand 1: the second operand of <op>, in the high bits of an i32
163 // for everything except ATOMIC_SWAPW
164 // Operand 2: how many bits to rotate the i32 left to bring the first
165 // operand into the high bits
166 // Operand 3: the negative of operand 2, for rotating the other way
167 // Operand 4: the width of the field in bits (8 or 16)
168 ATOMIC_SWAPW = ISD::FIRST_TARGET_MEMORY_OPCODE,
169 ATOMIC_LOADW_ADD,
170 ATOMIC_LOADW_SUB,
171 ATOMIC_LOADW_AND,
172 ATOMIC_LOADW_OR,
173 ATOMIC_LOADW_XOR,
174 ATOMIC_LOADW_NAND,
175 ATOMIC_LOADW_MIN,
176 ATOMIC_LOADW_MAX,
177 ATOMIC_LOADW_UMIN,
178 ATOMIC_LOADW_UMAX,
179
180 // A wrapper around the inner loop of an ATOMIC_CMP_SWAP.
181 //
182 // Operand 0: the address of the containing 32-bit-aligned field
183 // Operand 1: the compare value, in the low bits of an i32
184 // Operand 2: the swap value, in the low bits of an i32
185 // Operand 3: how many bits to rotate the i32 left to bring the first
186 // operand into the high bits
187 // Operand 4: the negative of operand 2, for rotating the other way
188 // Operand 5: the width of the field in bits (8 or 16)
189 ATOMIC_CMP_SWAPW,
190
191 // Prefetch from the second operand using the 4-bit control code in
192 // the first operand. The code is 1 for a load prefetch and 2 for
193 // a store prefetch.
194 PREFETCH
195 };
196
197 // Return true if OPCODE is some kind of PC-relative address.
isPCREL(unsigned Opcode)198 inline bool isPCREL(unsigned Opcode) {
199 return Opcode == PCREL_WRAPPER || Opcode == PCREL_OFFSET;
200 }
201 } // end namespace SystemZISD
202
203 namespace SystemZICMP {
204 // Describes whether an integer comparison needs to be signed or unsigned,
205 // or whether either type is OK.
206 enum {
207 Any,
208 UnsignedOnly,
209 SignedOnly
210 };
211 } // end namespace SystemZICMP
212
213 class SystemZSubtarget;
214 class SystemZTargetMachine;
215
216 class SystemZTargetLowering : public TargetLowering {
217 public:
218 explicit SystemZTargetLowering(const TargetMachine &TM,
219 const SystemZSubtarget &STI);
220
221 // Override TargetLowering.
getScalarShiftAmountTy(EVT LHSTy)222 MVT getScalarShiftAmountTy(EVT LHSTy) const override {
223 return MVT::i32;
224 }
225 EVT getSetCCResultType(LLVMContext &, EVT) const override;
226 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
227 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
228 bool isLegalICmpImmediate(int64_t Imm) const override;
229 bool isLegalAddImmediate(int64_t Imm) const override;
230 bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const override;
231 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS,
232 unsigned Align,
233 bool *Fast) const override;
234 bool isTruncateFree(Type *, Type *) const override;
235 bool isTruncateFree(EVT, EVT) const override;
236 const char *getTargetNodeName(unsigned Opcode) const override;
237 std::pair<unsigned, const TargetRegisterClass *>
238 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
239 const std::string &Constraint,
240 MVT VT) const override;
241 TargetLowering::ConstraintType
242 getConstraintType(const std::string &Constraint) const override;
243 TargetLowering::ConstraintWeight
244 getSingleConstraintMatchWeight(AsmOperandInfo &info,
245 const char *constraint) const override;
246 void LowerAsmOperandForConstraint(SDValue Op,
247 std::string &Constraint,
248 std::vector<SDValue> &Ops,
249 SelectionDAG &DAG) const override;
250
getInlineAsmMemConstraint(const std::string & ConstraintCode)251 unsigned getInlineAsmMemConstraint(
252 const std::string &ConstraintCode) const override {
253 if (ConstraintCode.size() == 1) {
254 switch(ConstraintCode[0]) {
255 default:
256 break;
257 case 'Q':
258 return InlineAsm::Constraint_Q;
259 case 'R':
260 return InlineAsm::Constraint_R;
261 case 'S':
262 return InlineAsm::Constraint_S;
263 case 'T':
264 return InlineAsm::Constraint_T;
265 }
266 }
267 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
268 }
269
270 MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
271 MachineBasicBlock *BB) const
272 override;
273 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
274 bool allowTruncateForTailCall(Type *, Type *) const override;
275 bool mayBeEmittedAsTailCall(CallInst *CI) const override;
276 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
277 bool isVarArg,
278 const SmallVectorImpl<ISD::InputArg> &Ins,
279 SDLoc DL, SelectionDAG &DAG,
280 SmallVectorImpl<SDValue> &InVals) const override;
281 SDValue LowerCall(CallLoweringInfo &CLI,
282 SmallVectorImpl<SDValue> &InVals) const override;
283
284 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
285 const SmallVectorImpl<ISD::OutputArg> &Outs,
286 const SmallVectorImpl<SDValue> &OutVals,
287 SDLoc DL, SelectionDAG &DAG) const override;
288 SDValue prepareVolatileOrAtomicLoad(SDValue Chain, SDLoc DL,
289 SelectionDAG &DAG) const override;
290 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
291
292 private:
293 const SystemZSubtarget &Subtarget;
294
295 // Implement LowerOperation for individual opcodes.
296 SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
297 SDValue lowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
298 SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
299 SDValue lowerGlobalAddress(GlobalAddressSDNode *Node,
300 SelectionDAG &DAG) const;
301 SDValue lowerTLSGetOffset(GlobalAddressSDNode *Node,
302 SelectionDAG &DAG, unsigned Opcode,
303 SDValue GOTOffset) const;
304 SDValue lowerGlobalTLSAddress(GlobalAddressSDNode *Node,
305 SelectionDAG &DAG) const;
306 SDValue lowerBlockAddress(BlockAddressSDNode *Node,
307 SelectionDAG &DAG) const;
308 SDValue lowerJumpTable(JumpTableSDNode *JT, SelectionDAG &DAG) const;
309 SDValue lowerConstantPool(ConstantPoolSDNode *CP, SelectionDAG &DAG) const;
310 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
311 SDValue lowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
312 SDValue lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
313 SDValue lowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
314 SDValue lowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
315 SDValue lowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;
316 SDValue lowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
317 SDValue lowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
318 SDValue lowerOR(SDValue Op, SelectionDAG &DAG) const;
319 SDValue lowerCTPOP(SDValue Op, SelectionDAG &DAG) const;
320 SDValue lowerATOMIC_LOAD(SDValue Op, SelectionDAG &DAG) const;
321 SDValue lowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) const;
322 SDValue lowerATOMIC_LOAD_OP(SDValue Op, SelectionDAG &DAG,
323 unsigned Opcode) const;
324 SDValue lowerATOMIC_LOAD_SUB(SDValue Op, SelectionDAG &DAG) const;
325 SDValue lowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
326 SDValue lowerLOAD_SEQUENCE_POINT(SDValue Op, SelectionDAG &DAG) const;
327 SDValue lowerSTACKSAVE(SDValue Op, SelectionDAG &DAG) const;
328 SDValue lowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const;
329 SDValue lowerPREFETCH(SDValue Op, SelectionDAG &DAG) const;
330 SDValue lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
331
332 // If the last instruction before MBBI in MBB was some form of COMPARE,
333 // try to replace it with a COMPARE AND BRANCH just before MBBI.
334 // CCMask and Target are the BRC-like operands for the branch.
335 // Return true if the change was made.
336 bool convertPrevCompareToBranch(MachineBasicBlock *MBB,
337 MachineBasicBlock::iterator MBBI,
338 unsigned CCMask,
339 MachineBasicBlock *Target) const;
340
341 // Implement EmitInstrWithCustomInserter for individual operation types.
342 MachineBasicBlock *emitSelect(MachineInstr *MI,
343 MachineBasicBlock *BB) const;
344 MachineBasicBlock *emitCondStore(MachineInstr *MI,
345 MachineBasicBlock *BB,
346 unsigned StoreOpcode, unsigned STOCOpcode,
347 bool Invert) const;
348 MachineBasicBlock *emitExt128(MachineInstr *MI,
349 MachineBasicBlock *MBB,
350 bool ClearEven, unsigned SubReg) const;
351 MachineBasicBlock *emitAtomicLoadBinary(MachineInstr *MI,
352 MachineBasicBlock *BB,
353 unsigned BinOpcode, unsigned BitSize,
354 bool Invert = false) const;
355 MachineBasicBlock *emitAtomicLoadMinMax(MachineInstr *MI,
356 MachineBasicBlock *MBB,
357 unsigned CompareOpcode,
358 unsigned KeepOldMask,
359 unsigned BitSize) const;
360 MachineBasicBlock *emitAtomicCmpSwapW(MachineInstr *MI,
361 MachineBasicBlock *BB) const;
362 MachineBasicBlock *emitMemMemWrapper(MachineInstr *MI,
363 MachineBasicBlock *BB,
364 unsigned Opcode) const;
365 MachineBasicBlock *emitStringWrapper(MachineInstr *MI,
366 MachineBasicBlock *BB,
367 unsigned Opcode) const;
368 MachineBasicBlock *emitTransactionBegin(MachineInstr *MI,
369 MachineBasicBlock *MBB,
370 unsigned Opcode,
371 bool NoFloat) const;
372 };
373 } // end namespace llvm
374
375 #endif
376