| /external/llvm/test/CodeGen/Mips/cconv/ |
| D | arguments-varargs.ll | 46 ; O32-DAG: addiu [[VA:\$[0-9]+]], [[SP]], 12
47 ; O32-DAG: sw [[VA]], 0([[SP]])
49 ; N32-DAG: addiu [[VA:\$[0-9]+]], [[SP]], 8
50 ; N32-DAG: sw [[VA]], 0([[SP]])
52 ; N64-DAG: daddiu [[VA:\$[0-9]+]], [[SP]], 8
53 ; N64-DAG: sd [[VA]], 0([[SP]])
55 ; Store [[VA]]
56 ; O32-DAG: sw [[VA]], 0([[SP]])
60 ; Increment [[VA]]
61 ; O32-DAG: lw [[VA:\$[0-9]+]], 0([[SP]])
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 206 CCValAssign &VA = RVLocs[i]; in LowerReturn_32() local
207 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn_32()
209 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), in LowerReturn_32()
214 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn_32()
268 CCValAssign &VA = RVLocs[i]; in LowerReturn_64() local
269 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn_64()
273 switch (VA.getLocInfo()) { in LowerReturn_64()
276 OutVal = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), OutVal); in LowerReturn_64()
279 OutVal = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), OutVal); in LowerReturn_64()
282 OutVal = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), OutVal); in LowerReturn_64()
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| /external/llvm/lib/Target/BPF/ |
| D | BPFISelLowering.cpp | 210 for (auto &VA : ArgLocs) { in LowerFormalArguments() local
211 if (VA.isRegLoc()) { in LowerFormalArguments()
213 EVT RegVT = VA.getLocVT(); in LowerFormalArguments()
222 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerFormalArguments()
228 if (VA.getLocInfo() == CCValAssign::SExt) in LowerFormalArguments()
230 DAG.getValueType(VA.getValVT())); in LowerFormalArguments()
231 else if (VA.getLocInfo() == CCValAssign::ZExt) in LowerFormalArguments()
233 DAG.getValueType(VA.getValVT())); in LowerFormalArguments()
235 if (VA.getLocInfo() != CCValAssign::Full) in LowerFormalArguments()
236 ArgValue = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), ArgValue); in LowerFormalArguments()
[all …]
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| /external/llvm/test/CodeGen/R600/ |
| D | madak.ll | 10 ; GCN: buffer_load_dword [[VA:v[0-9]+]]
12 ; GCN: v_madak_f32_e32 {{v[0-9]+}}, [[VB]], [[VA]], 0x41200000
33 ; GCN-DAG: buffer_load_dword [[VA:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr…
37 ; GCN-DAG: v_mad_f32 {{v[0-9]+}}, [[VA]], [[VB]], [[VK]]
38 ; GCN-DAG: v_mad_f32 {{v[0-9]+}}, [[VA]], [[VC]], [[VK]]
65 ; GCN: buffer_load_dword [[VA:v[0-9]+]]
66 ; GCN: v_madak_f32_e32 {{v[0-9]+}}, 4.0, [[VA]], 0x41200000
84 ; GCN: buffer_load_dword [[VA:v[0-9]+]]
86 ; GCN: v_mad_f32 {{v[0-9]+}}, [[VA]], [[VB]], 4.0
106 ; GCN-DAG: buffer_load_dword [[VA:v[0-9]+]]
[all …]
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| D | madmk.ll | 8 ; GCN-DAG: buffer_load_dword [[VA:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr…
10 ; GCN: v_madmk_f32_e32 {{v[0-9]+}}, [[VA]], [[VB]], 0x41200000
27 ; GCN-DAG: buffer_load_dword [[VA:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr…
31 ; GCN-DAG: v_mad_f32 {{v[0-9]+}}, [[VA]], [[VK]], [[VB]]
32 ; GCN-DAG: v_mad_f32 {{v[0-9]+}}, [[VA]], [[VK]], [[VC]]
60 ; GCN-DAG: buffer_load_dword [[VA:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr…
62 ; GCN: v_mad_f32 {{v[0-9]+}}, 4.0, [[VA]], [[VB]]
125 ; GCN-DAG: buffer_load_dword [[VA:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr…
146 ; GCN-DAG: buffer_load_dword [[VA:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr…
|
| D | llvm.AMDGPU.div_fmas.ll | 20 ; GCN-DAG: v_mov_b32_e32 [[VA:v[0-9]+]], [[SA]]
21 ; GCN: v_div_fmas_f32 [[RESULT:v[0-9]+]], [[VB]], [[VA]], [[VC]]
48 ; SI-DAG: v_mov_b32_e32 [[VA:v[0-9]+]], [[SA]]
49 ; SI: v_div_fmas_f32 [[RESULT:v[0-9]+]], 1.0, [[VA]], [[VC]]
61 ; SI-DAG: v_mov_b32_e32 [[VA:v[0-9]+]], [[SA]]
63 ; SI: v_div_fmas_f32 [[RESULT:v[0-9]+]], [[VA]], [[VB]], 1.0
|
| /external/clang/test/Parser/ |
| D | cxx-using-declaration.cpp | 4 int VA; variable
9 using A::VA;
15 VA = 1; in main()
|
| /external/clang/test/CXX/special/class.dtor/ |
| D | p3-0x.cpp | 140 struct VA { struct
142 virtual ~VA() {} in ~VA() argument
145 struct VB : VA
149 struct TVB : VA
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsFastISel.cpp | 960 CCValAssign &VA = ArgLocs[i]; in processCallArgs() local
961 const Value *ArgVal = CLI.OutVals[VA.getValNo()]; in processCallArgs()
962 MVT ArgVT = OutVTs[VA.getValNo()]; in processCallArgs()
967 VA.convertToReg(Mips::F12); in processCallArgs()
969 VA.convertToReg(Mips::D6); in processCallArgs()
974 VA.convertToReg(Mips::F14); in processCallArgs()
976 VA.convertToReg(Mips::D7); in processCallArgs()
980 if (((ArgVT == MVT::i32) || (ArgVT == MVT::f32)) && VA.isMemLoc()) { in processCallArgs()
981 switch (VA.getLocMemOffset()) { in processCallArgs()
983 VA.convertToReg(Mips::A0); in processCallArgs()
[all …]
|
| D | MipsISelLowering.cpp | 2593 CCValAssign &VA = ArgLocs[i]; in LowerCall() local
2594 MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT(); in LowerCall()
2611 VA); in LowerCall()
2617 switch (VA.getLocInfo()) { in LowerCall()
2621 if (VA.isRegLoc()) { in LowerCall()
2633 unsigned LocRegLo = VA.getLocReg(); in LowerCall()
2666 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); in LowerCall()
2668 ISD::SHL, DL, VA.getLocVT(), Arg, in LowerCall()
2669 DAG.getConstant(LocSizeInBits - ValSizeInBits, VA.getLocVT())); in LowerCall()
2674 if (VA.isRegLoc()) { in LowerCall()
[all …]
|
| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 454 CCValAssign &VA = ArgLocs[i]; in LowerCCCArguments() local
455 if (VA.isRegLoc()) { in LowerCCCArguments()
457 EVT RegVT = VA.getLocVT(); in LowerCCCArguments()
469 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerCCCArguments()
475 if (VA.getLocInfo() == CCValAssign::SExt) in LowerCCCArguments()
477 DAG.getValueType(VA.getValVT())); in LowerCCCArguments()
478 else if (VA.getLocInfo() == CCValAssign::ZExt) in LowerCCCArguments()
480 DAG.getValueType(VA.getValVT())); in LowerCCCArguments()
482 if (VA.getLocInfo() != CCValAssign::Full) in LowerCCCArguments()
483 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); in LowerCCCArguments()
[all …]
|
| /external/mksh/src/ |
| D | shf.c | 774 #define VA(type) va_arg(args, type) in shf_vfprintf() macro
823 tmp = VA(int); in shf_vfprintf()
884 lnum = (long)VA(ssize_t); in shf_vfprintf()
886 lnum = VA(long); in shf_vfprintf()
888 lnum = (long)(short)VA(int); in shf_vfprintf()
890 lnum = (long)VA(int); in shf_vfprintf()
897 lnum = VA(size_t); in shf_vfprintf()
899 lnum = VA(unsigned long); in shf_vfprintf()
901 lnum = (unsigned long)(unsigned short)VA(int); in shf_vfprintf()
903 lnum = (unsigned long)VA(unsigned int); in shf_vfprintf()
[all …]
|
| /external/clang/test/Preprocessor/ |
| D | macro_paste_bad.c | 32 #define VA __VA_ ## ARGS__ macro
33 int VA; // expected-warning {{__VA_ARGS__ can only appear in the expansion of a C99 variadic macr… variable
|
| /external/llvm/lib/Target/XCore/ |
| D | XCoreISelLowering.cpp | 1078 const CCValAssign &VA = RVLocs[i]; in LowerCallResult() local
1079 if (VA.isRegLoc()) { in LowerCallResult()
1080 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getValVT(), in LowerCallResult()
1085 assert(VA.isMemLoc()); in LowerCallResult()
1086 ResultMemLocs.push_back(std::make_pair(VA.getLocMemOffset(), in LowerCallResult()
1156 CCValAssign &VA = ArgLocs[i]; in LowerCCCCallTo() local
1160 switch (VA.getLocInfo()) { in LowerCCCCallTo()
1164 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCCCCallTo()
1167 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); in LowerCCCCallTo()
1170 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); in LowerCCCCallTo()
[all …]
|
| /external/skia/src/sfnt/ |
| D | SkOTTable_OS_2.h | 31 struct VA : SkOTTableOS2_VA { } vA; struct
45 SK_COMPILE_ASSERT(sizeof(SkOTTableOS2::Version::VA) == 68, sizeof_SkOTTableOS2__VA_not_68);
|
| /external/llvm/lib/Target/X86/ |
| D | X86FastISel.cpp | 1001 CCValAssign &VA = ValLocs[0]; in X86SelectRet() local
1004 if (VA.getLocInfo() != CCValAssign::Full) in X86SelectRet()
1007 if (!VA.isRegLoc()) in X86SelectRet()
1012 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) in X86SelectRet()
1015 unsigned SrcReg = Reg + VA.getValNo(); in X86SelectRet()
1017 EVT DstVT = VA.getValVT(); in X86SelectRet()
1041 unsigned DstReg = VA.getLocReg(); in X86SelectRet()
1050 RetRegs.push_back(VA.getLocReg()); in X86SelectRet()
2915 CCValAssign const &VA = ArgLocs[i]; in fastLowerCall() local
2916 const Value *ArgVal = OutVals[VA.getValNo()]; in fastLowerCall()
[all …]
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCFastISel.cpp | 1261 CCValAssign &VA = ArgLocs[I]; in processCallArgs() local
1262 MVT ArgVT = ArgVTs[VA.getValNo()]; in processCallArgs()
1267 !VA.isRegLoc() || VA.needsCustom()) in processCallArgs()
1271 if (VA.getLocInfo() == CCValAssign::BCvt) in processCallArgs()
1299 CCValAssign &VA = ArgLocs[I]; in processCallArgs() local
1300 unsigned Arg = ArgRegs[VA.getValNo()]; in processCallArgs()
1301 MVT ArgVT = ArgVTs[VA.getValNo()]; in processCallArgs()
1304 switch (VA.getLocInfo()) { in processCallArgs()
1310 MVT DestVT = VA.getLocVT(); in processCallArgs()
1322 MVT DestVT = VA.getLocVT(); in processCallArgs()
[all …]
|
| D | PPCInstrFormats.td | 1397 // E-1 VA-Form
1404 bits<5> VA;
1411 let Inst{11-15} = VA;
1422 bits<5> VA;
1429 let Inst{11-15} = VA;
1439 bits<5> VA;
1446 let Inst{11-15} = VA;
1458 bits<5> VA;
1464 let Inst{11-15} = VA;
1472 let VA = VD;
[all …]
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMFastISel.cpp | 1895 CCValAssign &VA = ArgLocs[i]; in ProcessCallArgs() local
1896 MVT ArgVT = ArgVTs[VA.getValNo()]; in ProcessCallArgs()
1903 if (VA.isRegLoc() && !VA.needsCustom()) { in ProcessCallArgs()
1905 } else if (VA.needsCustom()) { in ProcessCallArgs()
1907 if (VA.getLocVT() != MVT::f64 || in ProcessCallArgs()
1909 !VA.isRegLoc() || !ArgLocs[++i].isRegLoc()) in ProcessCallArgs()
1945 CCValAssign &VA = ArgLocs[i]; in ProcessCallArgs() local
1946 const Value *ArgVal = Args[VA.getValNo()]; in ProcessCallArgs()
1947 unsigned Arg = ArgRegs[VA.getValNo()]; in ProcessCallArgs()
1948 MVT ArgVT = ArgVTs[VA.getValNo()]; in ProcessCallArgs()
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| D | ARMISelLowering.cpp | 1345 CCValAssign VA = RVLocs[i]; in LowerCallResult() local
1350 assert(!VA.needsCustom() && VA.getLocVT() == MVT::i32 && in LowerCallResult()
1357 if (VA.needsCustom()) { in LowerCallResult()
1359 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, in LowerCallResult()
1363 VA = RVLocs[++i]; // skip ahead to next loc in LowerCallResult()
1364 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, in LowerCallResult()
1372 if (VA.getLocVT() == MVT::v2f64) { in LowerCallResult()
1377 VA = RVLocs[++i]; // skip ahead to next loc in LowerCallResult()
1378 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag); in LowerCallResult()
1381 VA = RVLocs[++i]; // skip ahead to next loc in LowerCallResult()
[all …]
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZISelLowering.cpp | 651 CCValAssign &VA, SDValue Chain, in convertLocVTToValVT() argument
655 if (VA.getLocInfo() == CCValAssign::SExt) in convertLocVTToValVT()
656 Value = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Value, in convertLocVTToValVT()
657 DAG.getValueType(VA.getValVT())); in convertLocVTToValVT()
658 else if (VA.getLocInfo() == CCValAssign::ZExt) in convertLocVTToValVT()
659 Value = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Value, in convertLocVTToValVT()
660 DAG.getValueType(VA.getValVT())); in convertLocVTToValVT()
662 if (VA.isExtInLoc()) in convertLocVTToValVT()
663 Value = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Value); in convertLocVTToValVT()
664 else if (VA.getLocInfo() == CCValAssign::Indirect) in convertLocVTToValVT()
[all …]
|
| /external/llvm/tools/llvm-readobj/ |
| D | ARMWinEHPrinter.cpp | 187 Decoder::getSectionContaining(const COFFObjectFile &COFF, uint64_t VA) { in getSectionContaining() argument
192 if (VA >= Address && (VA - Address) <= Size) in getSectionContaining()
199 uint64_t VA, bool FunctionOnly) { in getSymbol() argument
212 if (Address == VA) in getSymbol()
518 uint64_t FunctionAddress, uint64_t VA) { in dumpXDataRecord() argument
524 uint64_t Offset = VA - SectionVA; in dumpXDataRecord()
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 349 CCValAssign &VA = RVLocs[i]; in LowerReturn() local
351 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag); in LowerReturn()
355 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
461 CCValAssign &VA = ArgLocs[i]; in LowerCall() local
462 if (VA.isMemLoc()) { in LowerCall()
485 CCValAssign &VA = ArgLocs[i]; in LowerCall() local
490 switch (VA.getLocInfo()) { in LowerCall()
497 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
500 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
503 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
[all …]
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| /external/clang/lib/Analysis/ |
| D | LiveVariables.cpp | 292 for (const VariableArrayType* VA = FindVA(VD->getType()); in Visit() local
293 VA != nullptr; VA = FindVA(VA->getElementType())) { in Visit()
294 AddLiveStmt(val.liveStmts, LV.SSetFact, VA->getSizeExpr()); in Visit()
|
| /external/llvm/test/CodeGen/ARM/ |
| D | 2013-04-21-AAPCS-VA-C.1.cp.ll | 1 ;Check 5.5 Parameter Passing --> Stage C --> C.1.cp statement for VA functions.
|