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Searched refs:extr (Results 1 – 25 of 28) sorted by relevance

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/external/llvm/test/MC/AArch64/
Darm64-bitfield-encoding.s34 extr w1, w2, w3, #15
35 extr x2, x3, x4, #1
37 ; CHECK: extr w1, w2, w3, #15 ; encoding: [0x41,0x3c,0x83,0x13]
38 ; CHECK: extr x2, x3, x4, #1 ; encoding: [0x62,0x04,0xc4,0x93]
Dbasic-a64-diagnostics.s1485 extr w2, w20, w30, #-1
1486 extr w9, w19, w20, #32
1494 extr x10, x15, x20, #-1
1495 extr x20, x25, x30, #64
Dbasic-a64-instructions.s1727 extr w3, w5, w7, #0
1728 extr w11, w13, w17, #31
1732 extr x3, x5, x7, #15
1733 extr x11, x13, x17, #63
/external/valgrind/none/tests/arm64/
Dinteger.stdout.exp335 extr x3, x4, x5, #0 :: rd a6325ae016fbd710 rm db432311d1e3a1d0, rn a6325ae016fbd710, cin 0, nzcv 00…
336 extr x3, x4, x5, #0 :: rd fd370f11bfcd4a4a rm 192e7217e1ab63b0, rn fd370f11bfcd4a4a, cin 0, nzcv 00…
337 extr x3, x4, x5, #0 :: rd 5bc94f0d3ee4863a rm fd79baaee550b488, rn 5bc94f0d3ee4863a, cin 0, nzcv 00…
338 extr x3, x4, x5, #0 :: rd e861540945421773 rm c58586ea2c6954df, rn e861540945421773, cin 0, nzcv 00…
339 extr x3, x4, x5, #0 :: rd 507865169b052546 rm e51579fec3892795, rn 507865169b052546, cin 0, nzcv 00…
340 extr x3, x4, x5, #0 :: rd 9a1140d0fd1dbf6c rm 1b834ed5b21de6b5, rn 9a1140d0fd1dbf6c, cin 0, nzcv 00…
341 extr x3, x4, x5, #1 :: rd 53192d700b7deb88 rm db432311d1e3a1d0, rn a6325ae016fbd710, cin 0, nzcv 00…
342 extr x3, x4, x5, #1 :: rd 7e9b8788dfe6a525 rm 192e7217e1ab63b0, rn fd370f11bfcd4a4a, cin 0, nzcv 00…
343 extr x3, x4, x5, #1 :: rd 2de4a7869f72431d rm fd79baaee550b488, rn 5bc94f0d3ee4863a, cin 0, nzcv 00…
344 extr x3, x4, x5, #1 :: rd f430aa04a2a10bb9 rm c58586ea2c6954df, rn e861540945421773, cin 0, nzcv 00…
[all …]
/external/llvm/test/CodeGen/AArch64/
Darm64-extract.ll1 ; RUN: llc -aarch64-extr-generation=true -verify-machineinstrs < %s \
29 ; CHECK: extr {{w[0-9]+}}, w0, w1, #26
41 ; CHECK: extr {{x[0-9]+}}, x0, x1, #40
54 ; CHECK-NOT: extr {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, #{{[0-9]+}}
Dextract.ll28 ; CHECK: extr {{w[0-9]+}}, w0, w1, #26
40 ; CHECK: extr {{x[0-9]+}}, x0, x1, #40
53 ; CHECK-NOT: extr {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, #{{[0-9]+}}
Darm64-andCmpBrToTBZ.ll2 ; ModuleID = 'and-cbz-extr-mr.bc'
/external/llvm/test/MC/Disassembler/AArch64/
Darm64-bitfield.txt28 # CHECK: extr w1, w2, w3, #15
29 # CHECK: extr x2, x3, x4, #1
Dbasic-a64-instructions.txt1298 # CHECK: extr w3, w5, w7, #0
1299 # CHECK: extr w11, w13, w17, #31
1303 # CHECK: extr x3, x5, x7, #15
1304 # CHECK: extr x11, x13, x17, #63
/external/llvm/test/CodeGen/Mips/
Ddsp-r1.ll5 ; CHECK: extr.w
7 %1 = tail call i32 @llvm.mips.extr.w(i64 %a0, i32 15)
11 declare i32 @llvm.mips.extr.w(i64, i32) nounwind
17 %1 = tail call i32 @llvm.mips.extr.w(i64 %a0, i32 %a1)
25 %1 = tail call i32 @llvm.mips.extr.r.w(i64 %a0, i32 15)
29 declare i32 @llvm.mips.extr.r.w(i64, i32) nounwind
35 %1 = tail call i32 @llvm.mips.extr.s.h(i64 %a0, i32 %a1)
39 declare i32 @llvm.mips.extr.s.h(i64, i32) nounwind
45 %1 = tail call i32 @llvm.mips.extr.rs.w(i64 %a0, i32 15)
49 declare i32 @llvm.mips.extr.rs.w(i64, i32) nounwind
[all …]
/external/libunwind/src/ia64/
Dgetcontext.S112 extr.u rPOS = rPOS, 3, 6 // get NaT bitnr for r0 // I0
/external/vixl/doc/
Dchangelog.md55 + Fix simulation of `extr` instruction.
Dsupported-instructions.md488 void extr(const Register& rd,
/external/v8/test/cctest/
Dtest-disasm-arm64.cc560 COMPARE(extr(w0, w1, w2, 0), "extr w0, w1, w2, #0"); in TEST_()
561 COMPARE(extr(x3, x4, x5, 1), "extr x3, x4, x5, #1"); in TEST_()
562 COMPARE(extr(w6, w7, w8, 31), "extr w6, w7, w8, #31"); in TEST_()
563 COMPARE(extr(x9, x10, x11, 63), "extr x9, x10, x11, #63"); in TEST_()
564 COMPARE(extr(w12, w13, w13, 10), "ror w12, w13, #10"); in TEST_()
565 COMPARE(extr(x14, x15, x15, 42), "ror x14, x15, #42"); in TEST_()
/external/valgrind/none/tests/mips32/
Dmips32_dsp.stdout.exp-BE1267 extr.w $t4, $ac3, 0 :: rt 0x00000000 ac3 0x0000000000000000 size 0 DSPCtrl 0x00000000
1268 extr.w $t5, $ac0, 31 :: rt 0xffffffff ac0 0x7fffffffcbcdef01 size 31 DSPCtrl 0x00800000
1269 extr.w $t6, $ac1, 31 :: rt 0x7ffffffe ac1 0x3fffffff2bcdef01 size 31 DSPCtrl 0x00000000
1270 extr.w $t7, $ac2, 0 :: rt 0xffffffff ac2 0xffffffffffffffff size 0 DSPCtrl 0x00000000
1271 extr.w $t8, $ac3, 1 :: rt 0x7fffffff ac3 0x00000000fffffffe size 1 DSPCtrl 0x00000000
1272 extr.w $t1, $ac0, 31 :: rt 0x00000001 ac0 0x8000000080000000 size 31 DSPCtrl 0x00800000
1273 extr.w $t2, $ac1, 17 :: rt 0x0000c000 ac1 0x8000000180000002 size 17 DSPCtrl 0x00800000
1274 extr.w $t3, $ac2, 4 :: rt 0x00000000 ac2 0x0000000000000006 size 4 DSPCtrl 0x00000000
1275 extr.w $t4, $ac3, 12 :: rt 0x00440000 ac3 0x0000000440000000 size 12 DSPCtrl 0x00000000
1276 extr.w $t5, $ac0, 3 :: rt 0xefffffff ac0 0x7fffffff7fffffff size 3 DSPCtrl 0x00800000
[all …]
Dmips32_dsp.stdout.exp-LE1267 extr.w $t4, $ac3, 0 :: rt 0x00000000 ac3 0x0000000000000000 size 0 DSPCtrl 0x00000000
1268 extr.w $t5, $ac0, 31 :: rt 0xffffffff ac0 0x7fffffffcbcdef01 size 31 DSPCtrl 0x00800000
1269 extr.w $t6, $ac1, 31 :: rt 0x7ffffffe ac1 0x3fffffff2bcdef01 size 31 DSPCtrl 0x00000000
1270 extr.w $t7, $ac2, 0 :: rt 0xffffffff ac2 0xffffffffffffffff size 0 DSPCtrl 0x00000000
1271 extr.w $t8, $ac3, 1 :: rt 0x7fffffff ac3 0x00000000fffffffe size 1 DSPCtrl 0x00000000
1272 extr.w $t1, $ac0, 31 :: rt 0x00000001 ac0 0x8000000080000000 size 31 DSPCtrl 0x00800000
1273 extr.w $t2, $ac1, 17 :: rt 0x0000c000 ac1 0x8000000180000002 size 17 DSPCtrl 0x00800000
1274 extr.w $t3, $ac2, 4 :: rt 0x00000000 ac2 0x0000000000000006 size 4 DSPCtrl 0x00000000
1275 extr.w $t4, $ac3, 12 :: rt 0x00440000 ac3 0x0000000440000000 size 12 DSPCtrl 0x00000000
1276 extr.w $t5, $ac0, 3 :: rt 0xefffffff ac0 0x7fffffff7fffffff size 3 DSPCtrl 0x00800000
[all …]
/external/v8/src/arm64/
Dassembler-arm64.h1327 void extr(const Register& rd,
1373 extr(rd, rs, rs, shift); in ror()
Dmacro-assembler-arm64-inl.h538 extr(rd, rn, rm, lsb); in Extr()
Dassembler-arm64.cc1316 void Assembler::extr(const Register& rd, in extr() function in v8::internal::Assembler
/external/vixl/test/
Dtest-disasm-a64.cc659 COMPARE(extr(w0, w1, w2, 0), "extr w0, w1, w2, #0"); in TEST()
660 COMPARE(extr(x3, x4, x5, 1), "extr x3, x4, x5, #1"); in TEST()
661 COMPARE(extr(w6, w7, w8, 31), "extr w6, w7, w8, #31"); in TEST()
662 COMPARE(extr(x9, x10, x11, 63), "extr x9, x10, x11, #63"); in TEST()
663 COMPARE(extr(w12, w13, w13, 10), "ror w12, w13, #10"); in TEST()
664 COMPARE(extr(x14, x15, x15, 42), "ror x14, x15, #42"); in TEST()
/external/vixl/src/vixl/a64/
Dassembler-a64.h1471 void extr(const Register& rd,
1517 extr(rd, rs, rs, shift); in ror()
Dmacro-assembler-a64.h1139 extr(rd, rn, rm, lsb); in Extr()
Dassembler-a64.cc1088 void Assembler::extr(const Register& rd, in extr() function in vixl::Assembler
/external/llvm/lib/Target/Mips/
DMipsDSPInstrInfo.td860 class EXTR_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr.w", MipsEXTR_W, NoItinerary>,
/external/svox/pico_resources/tools/LingwareBuilding/PicoLingware_source_files/textana/fr-FR/
Dfr-FR_lexpos.utf786 ADJ_SG^N_ADJ_F_SG "extrême" :G2P

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