1VIXL Change Log 2=============== 3 4* 1.9 5 + Improved compatibility with Android build system. 6 + Improved compatibility with Clang toolchain. 7 + Added support for `umulh` instruction. 8 + Added support for `fcmpe` and `fccmpe` instructions. 9 + Other small bug fixes and improvements. 10 11* 1.8 12 + Complete NEON instruction set support. 13 + Support long branches using veneers. 14 + Improved handling of literal pools. 15 + Support some `ic` and `dc` cache op instructions. 16 + Support CRC32 instructions. 17 + Support half-precision floating point instructions. 18 + MacroAssembler support for `bfm`, `ubfm` and `sbfm`. 19 + Other small bug fixes and improvements. 20 21* 1.7 22 + Added support for `prfm` prefetch instructions. 23 + Added support for all `frint` instruction variants. 24 + Add support for disassembling as an offset from a given address. 25 + Fixed the disassembly of `movz` and `movn`. 26 + Provide static helpers for immediate generation. 27 + Provide helpers to create CPURegList from list unions or intersections. 28 + Improved register value tracing. 29 + Multithreading test fixes. 30 + Other small bug fixes and build system improvements. 31 32* 1.6 33 + Make literal pool management the responsibility of the macro assembler. 34 + Move code buffer management out of the Assembler. 35 + Support `ldrsw` for literals. 36 + Support binding a label to a specific offset. 37 + Add macro assembler support for load/store pair with arbitrary offset. 38 + Support Peek and Poke for CPURegLists. 39 + Fix disassembly of branch targets. 40 + Fix Decoder visitor insertion order. 41 + Separate Decoder visitors into const and non-const variants. 42 + Fix simulator for branches to tagged addresses. 43 + Add a VIM YouCompleteMe configuration file. 44 + Other small bug fixes and build system improvements. 45 46* 1.5 47 + Tagged pointer support. 48 + Implement support for exclusive access instructions. 49 + Implement support for `adrp` instruction. 50 + Faster code for logical immediate identification. 51 + Generate better code for immediates passed to shift-capable instructions. 52 + Allow explicit use of unscaled-offset loads and stores. 53 + Build and test infrastructure improvements. 54 + Corrected computation of cache line size. 55 + Fix simulation of `extr` instruction. 56 + Fixed a bug when moving kWMinInt to a register. 57 + Other small bug fixes. 58 59* 1.4 60 + Added support for `frintm`. 61 + Fixed simulation of `frintn` and `frinta` for corner cases. 62 + Added more tests for floating point instruction simulation. 63 + Modified `CalleeSave()` and `CalleeRestore()` to push general purpose 64 registers before floating point registers on the stack. 65 + Fixed Printf for mixed argument types, and use on real hardware. 66 + Improved compatibility with some 32-bit compilers. 67 68* 1.3 69 + Address inaccuracies in the simulated floating point instructions. 70 + Implement Default-NaN floating point mode. 71 + Introduce `UseScratchRegisterScope` for controlling the use of temporary 72 registers. 73 + Enable building VIXL on 32-bit hosts. 74 + Other small bug fixes and improvements. 75 76* 1.2 77 + Added support for `fmadd`, `fnmadd`, `fnmsub`, `fminnm`, `fmaxnm`, 78 `frinta`, `fcvtau` and `fcvtas`. 79 + Added support for assembling and disassembling `isb`, `dsb` and `dmb`. 80 + Added support for automatic inversion of compare instructions when using 81 negative immediates. 82 + Added support for using `movn` when generating immediates. 83 + Added explicit flag-setting 'S' instructions, and removed 84 `SetFlags` and `LeaveFlags` arguments. 85 + Added support for `Movk` in macro assembler. 86 + Added support for W register parameters to `Tbz` and `Tbnz`. 87 + Added support for using immediate operands with `Csel`. 88 + Added new debugger syntax for memory inspection. 89 + Fixed `smull`, `fmsub` and `sdiv` simulation. 90 + Fixed sign extension for W->X conversions using `sxtb`, `sxth` and `sxtw`. 91 + Prevented code generation for certain side-effect free operations, 92 such as `add r, r, #0`, in the macro assembler. 93 + Other small bug fixes. 94 95* 1.1 96 + Improved robustness of instruction decoder and disassembler. 97 + Added support for double-to-float conversions using `fcvt`. 98 + Added support for more fixed-point to floating-point conversions (`ucvtf` 99 and `scvtf`). 100 + Added instruction statistics collection class `instrument-a64.cc`. 101 102* 1.0 103 + Initial release. 104