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/external/llvm/test/CodeGen/X86/
D2009-11-13-VirtRegRewriterBug.ll9 %mask133.masked.masked.masked.masked.masked.masked = or i640 undef, undef ; <i640> [#uses=1]
31 %mask271.masked.masked.masked.masked.masked.masked.masked = or i256 0, undef ; <i256> [#uses=2]
32 …%mask266.masked.masked.masked.masked.masked.masked = or i256 %mask271.masked.masked.masked.masked.…
33 %mask241.masked = or i256 undef, undef ; <i256> [#uses=1]
53 …%tmp211 = lshr i256 %mask271.masked.masked.masked.masked.masked.masked.masked, 112 ; <i256> [#uses…
55 %tmp208 = lshr i256 %mask266.masked.masked.masked.masked.masked.masked, 128 ; <i256> [#uses=1]
60 %tmp193 = lshr i256 %mask241.masked, 208 ; <i256> [#uses=1]
97 %tmp101 = lshr i640 %mask133.masked.masked.masked.masked.masked.masked, 256 ; <i640> [#uses=1]
Dmasked_memop.ll15 ; AVX_SCALAR-NOT: masked
22 …%res = call <16 x i32> @llvm.masked.load.v16i32(<16 x i32>* %addr, i32 4, <16 x i1>%mask, <16 x i3…
35 …%res = call <16 x i32> @llvm.masked.load.v16i32(<16 x i32>* %addr, i32 4, <16 x i1>%mask, <16 x i3…
43 ; AVX_SCALAR-NOT: masked
52 call void @llvm.masked.store.v16i32(<16 x i32>%val, <16 x i32>* %addr, i32 4, <16 x i1>%mask)
65 …%res = call <16 x float> @llvm.masked.load.v16f32(<16 x float>* %addr, i32 4, <16 x i1>%mask, <16 …
79 …%res = call <8 x double> @llvm.masked.load.v8f64(<8 x double>* %addr, i32 4, <8 x i1>%mask, <8 x d…
91 …%res = call <2 x double> @llvm.masked.load.v2f64(<2 x double>* %addr, i32 4, <2 x i1>%mask, <2 x d…
103 …%res = call <4 x float> @llvm.masked.load.v4f32(<4 x float>* %addr, i32 4, <4 x i1>%mask, <4 x flo…
115 …%res = call <4 x i32> @llvm.masked.load.v4i32(<4 x i32>* %addr, i32 4, <4 x i1>%mask, <4 x i32>%ds…
[all …]
Dnarrow-shl-load.ll19 %shl15.masked = and i64 %shl15, 4294967294
20 %and17 = or i64 %shl15.masked, %conv11
/external/llvm/test/Analysis/CostModel/X86/
Dmasked-intrinsic-cost.ll5 ; AVX2: Found an estimated cost of 4 {{.*}}.masked
8 …%res = call <2 x double> @llvm.masked.load.v2f64(<2 x double>* %addr, i32 4, <2 x i1>%mask, <2 x d…
13 ; AVX2: Found an estimated cost of 4 {{.*}}.masked
16 …%res = call <4 x i32> @llvm.masked.load.v4i32(<4 x i32>* %addr, i32 4, <4 x i1>%mask, <4 x i32>%ds…
21 ; AVX2: Found an estimated cost of 4 {{.*}}.masked
24 call void @llvm.masked.store.v4i32(<4 x i32>%val, <4 x i32>* %addr, i32 4, <4 x i1>%mask)
29 ; AVX2: Found an estimated cost of 4 {{.*}}.masked
32 …%res = call <8 x float> @llvm.masked.load.v8f32(<8 x float>* %addr, i32 4, <8 x i1>%mask, <8 x flo…
37 ; AVX2: Found an estimated cost of 5 {{.*}}.masked
40 call void @llvm.masked.store.v2f32(<2 x float>%val, <2 x float>* %addr, i32 4, <2 x i1>%mask)
[all …]
/external/llvm/test/CodeGen/PowerPC/
Drlwimi-dyn-and.ll17 %shl161.masked = and i32 %shl161, %const_mat
18 %conv174 = or i32 %shl170, %shl161.masked
37 %shl161.masked = and i32 %shl161, 32768
38 %conv174 = or i32 %shl170, %shl161.masked
Drlwinm2.ll25 %tmp2.masked = and i32 %tmp2, 96 ; <i32> [#uses=1]
26 %tmp5 = or i32 %tmp1, %tmp2.masked ; <i32> [#uses=1]
/external/llvm/test/Transforms/LoopVectorize/X86/
Dmasked_load_store.ll5 ;AVX1-NOT: llvm.masked
23 ;AVX2: call <8 x i32> @llvm.masked.load.v8i32
25 ;AVX2: call void @llvm.masked.store.v8i32
30 ;AVX512: call <16 x i32> @llvm.masked.load.v16i32
32 ;AVX512: call void @llvm.masked.store.v16i32
107 ;AVX2: call <8 x float> @llvm.masked.load.v8f32
109 ;AVX2: call void @llvm.masked.store.v8f32
114 ;AVX512: call <16 x float> @llvm.masked.load.v16f32
116 ;AVX512: call void @llvm.masked.store.v16f32
192 ;AVX2: call <4 x double> @llvm.masked.load.v4f64
[all …]
/external/llvm/test/Transforms/ConstantHoisting/PowerPC/
Dmasks.ll25 %shl161.masked = and i32 %shl161, 32768
26 %conv174 = or i32 %shl170, %shl161.masked
55 %shl161.masked = and i32 %shl161, 32773
56 %conv174 = or i32 %shl170, %shl161.masked
/external/llvm/test/Transforms/InstCombine/
Dicmp-logical.ll131 %masked = and i32 %in, 1
132 %tst2 = icmp eq i32 %masked, 0
145 %masked = and i32 %in, 1
146 %tst1 = icmp eq i32 %masked, 0
D2013-03-05-Combine-BitcastTy-Into-Alloca.ll27 %bf.value.masked = and i96 %bf.value, 4294967232
30 %bf.clear4 = or i96 %bf.shl3, %bf.value.masked
/external/llvm/test/CodeGen/Thumb2/
Dbfi.ll58 %b.masked = and i32 %b, -2
59 %and3 = or i32 %b.masked, %and
/external/mesa3d/src/gallium/auxiliary/gallivm/
Dlp_bld_swizzle.c402 LLVMValueRef masked; in lp_build_swizzle_aos() local
408 masked = LLVMBuildAnd(builder, a, in lp_build_swizzle_aos()
411 shifted = LLVMBuildShl(builder, masked, in lp_build_swizzle_aos()
414 shifted = LLVMBuildLShr(builder, masked, in lp_build_swizzle_aos()
417 shifted = masked; in lp_build_swizzle_aos()
Dlp_bld_format_aos.c154 LLVMValueRef shifted, casted, scaled, masked; in lp_build_unpack_arith_rgba_aos() local
230 masked = LLVMBuildAnd(builder, shifted, LLVMConstVector(masks, 4), ""); in lp_build_unpack_arith_rgba_aos()
235 …casted = LLVMBuildSIToFP(builder, masked, LLVMVectorType(LLVMFloatTypeInContext(gallivm->context),… in lp_build_unpack_arith_rgba_aos()
237 …casted = LLVMBuildUIToFP(builder, masked, LLVMVectorType(LLVMFloatTypeInContext(gallivm->context),… in lp_build_unpack_arith_rgba_aos()
/external/llvm/test/CodeGen/AArch64/
Dbitfield.ll185 %masked = and i32 %shifted, 7
186 ret i32 %masked
194 %masked = and i64 %shifted, 1023
195 ret i64 %masked
Dbitfield-insert.ll17 %f.sroa.0.0.insert.ext.masked = and i32 %tmp.sroa.0.0.extract.trunc, 135
18 %1 = or i32 %f.sroa.0.0.insert.ext.masked, %0
/external/jetty/src/java/org/eclipse/jetty/websocket/
DWebSocketParserD06.java80 …c WebSocketParserD06(WebSocketBuffers buffers, EndPoint endp, FrameHandler handler, boolean masked) in WebSocketParserD06() argument
85 _masked=masked; in WebSocketParserD06()
/external/libvncserver/test/
Dcursortest.c257 rfbBool masked=(c->mask[(i/8)+maskStride*j]<<(i&7))&0x80; in SetAlphaCursor() local
258 c->alphaSource[i+c->width*j]=(masked?(mode==1?value:0xff-value):0); in SetAlphaCursor()
/external/valgrind/gdbserver_tests/
Dnlsigvgdb.vgtest4 # But if this signal is masked, then vgdb does not recuperate the control
/external/llvm/test/Transforms/LoopStrengthReduce/AArch64/
Dlsr-memset.ll60 %mask2.masked = or i64 %mask5, %6
61 %mask = or i64 %mask2.masked, %7
/external/llvm/test/Transforms/SimplifyCFG/
DCoveredLookupTable.ll14 ; CHECK-NEXT: ret i3 %switch.masked
/external/deqp/modules/gles2/functional/
Des2fDepthStencilClearTests.cpp121 …ar* description, int numIters, int numClears, bool depth, bool stencil, bool scissor, bool masked);
145 …har* description, int numIters, int numClears, bool depth, bool stencil, bool scissor, bool masked) in DepthStencilClearCase() argument
150 , m_masked (masked) in DepthStencilClearCase()
/external/deqp/modules/gles3/functional/
Des3fDepthStencilClearTests.cpp121 …ar* description, int numIters, int numClears, bool depth, bool stencil, bool scissor, bool masked);
145 …har* description, int numIters, int numClears, bool depth, bool stencil, bool scissor, bool masked) in DepthStencilClearCase() argument
150 , m_masked (masked) in DepthStencilClearCase()
/external/nanohttpd/websocket/src/main/java/fi/iki/elonen/
DWebSocketFrame.java179 boolean masked = ((b & 0x80) != 0); in readPayloadInfo()
212 if (masked) { in readPayloadInfo()
/external/llvm/test/MC/Mips/
Dnacl-mask.s98 # are not masked.
160 # are not masked.
/external/llvm/test/CodeGen/R600/
Dtrunc-cmp-constant.ll165 %masked = and i8 %load, 255
166 %ext = sext i8 %masked to i32

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