1; RUN: llc -mtriple=x86_64-apple-darwin -mcpu=knl < %s | FileCheck %s -check-prefix=AVX512 2; RUN: llc -mtriple=x86_64-apple-darwin -mcpu=core-avx2 < %s | FileCheck %s -check-prefix=AVX2 3; RUN: opt -mtriple=x86_64-apple-darwin -codegenprepare -mcpu=corei7-avx -S < %s | FileCheck %s -check-prefix=AVX_SCALAR 4; RUN: llc -mtriple=x86_64-apple-darwin -mcpu=skx < %s | FileCheck %s -check-prefix=SKX 5 6; AVX512-LABEL: test1 7; AVX512: vmovdqu32 (%rdi), %zmm0 {%k1} {z} 8 9; AVX2-LABEL: test1 10; AVX2: vpmaskmovd 32(%rdi) 11; AVX2: vpmaskmovd (%rdi) 12; AVX2-NOT: blend 13 14; AVX_SCALAR-LABEL: test1 15; AVX_SCALAR-NOT: masked 16; AVX_SCALAR: extractelement 17; AVX_SCALAR: insertelement 18; AVX_SCALAR: extractelement 19; AVX_SCALAR: insertelement 20define <16 x i32> @test1(<16 x i32> %trigger, <16 x i32>* %addr) { 21 %mask = icmp eq <16 x i32> %trigger, zeroinitializer 22 %res = call <16 x i32> @llvm.masked.load.v16i32(<16 x i32>* %addr, i32 4, <16 x i1>%mask, <16 x i32>undef) 23 ret <16 x i32> %res 24} 25 26; AVX512-LABEL: test2 27; AVX512: vmovdqu32 (%rdi), %zmm0 {%k1} {z} 28 29; AVX2-LABEL: test2 30; AVX2: vpmaskmovd {{.*}}(%rdi) 31; AVX2: vpmaskmovd {{.*}}(%rdi) 32; AVX2-NOT: blend 33define <16 x i32> @test2(<16 x i32> %trigger, <16 x i32>* %addr) { 34 %mask = icmp eq <16 x i32> %trigger, zeroinitializer 35 %res = call <16 x i32> @llvm.masked.load.v16i32(<16 x i32>* %addr, i32 4, <16 x i1>%mask, <16 x i32>zeroinitializer) 36 ret <16 x i32> %res 37} 38 39; AVX512-LABEL: test3 40; AVX512: vmovdqu32 %zmm1, (%rdi) {%k1} 41 42; AVX_SCALAR-LABEL: test3 43; AVX_SCALAR-NOT: masked 44; AVX_SCALAR: extractelement 45; AVX_SCALAR: store 46; AVX_SCALAR: extractelement 47; AVX_SCALAR: store 48; AVX_SCALAR: extractelement 49; AVX_SCALAR: store 50define void @test3(<16 x i32> %trigger, <16 x i32>* %addr, <16 x i32> %val) { 51 %mask = icmp eq <16 x i32> %trigger, zeroinitializer 52 call void @llvm.masked.store.v16i32(<16 x i32>%val, <16 x i32>* %addr, i32 4, <16 x i1>%mask) 53 ret void 54} 55 56; AVX512-LABEL: test4 57; AVX512: vmovups (%rdi), %zmm{{.*{%k[1-7]}}} 58 59; AVX2-LABEL: test4 60; AVX2: vmaskmovps {{.*}}(%rdi) 61; AVX2: vmaskmovps {{.*}}(%rdi) 62; AVX2: blend 63define <16 x float> @test4(<16 x i32> %trigger, <16 x float>* %addr, <16 x float> %dst) { 64 %mask = icmp eq <16 x i32> %trigger, zeroinitializer 65 %res = call <16 x float> @llvm.masked.load.v16f32(<16 x float>* %addr, i32 4, <16 x i1>%mask, <16 x float> %dst) 66 ret <16 x float> %res 67} 68 69; AVX512-LABEL: test5 70; AVX512: vmovupd (%rdi), %zmm1 {%k1} 71 72; AVX2-LABEL: test5 73; AVX2: vmaskmovpd 74; AVX2: vblendvpd 75; AVX2: vmaskmovpd 76; AVX2: vblendvpd 77define <8 x double> @test5(<8 x i32> %trigger, <8 x double>* %addr, <8 x double> %dst) { 78 %mask = icmp eq <8 x i32> %trigger, zeroinitializer 79 %res = call <8 x double> @llvm.masked.load.v8f64(<8 x double>* %addr, i32 4, <8 x i1>%mask, <8 x double>%dst) 80 ret <8 x double> %res 81} 82 83; AVX2-LABEL: test6 84; AVX2: vmaskmovpd 85; AVX2: vblendvpd 86 87; SKX-LABEL: test6 88; SKX: vmovupd {{.*}}{%k1} 89define <2 x double> @test6(<2 x i64> %trigger, <2 x double>* %addr, <2 x double> %dst) { 90 %mask = icmp eq <2 x i64> %trigger, zeroinitializer 91 %res = call <2 x double> @llvm.masked.load.v2f64(<2 x double>* %addr, i32 4, <2 x i1>%mask, <2 x double>%dst) 92 ret <2 x double> %res 93} 94 95; AVX2-LABEL: test7 96; AVX2: vmaskmovps {{.*}}(%rdi) 97; AVX2: blend 98 99; SKX-LABEL: test7 100; SKX: vmovups (%rdi){{.*}}{%k1} 101define <4 x float> @test7(<4 x i32> %trigger, <4 x float>* %addr, <4 x float> %dst) { 102 %mask = icmp eq <4 x i32> %trigger, zeroinitializer 103 %res = call <4 x float> @llvm.masked.load.v4f32(<4 x float>* %addr, i32 4, <4 x i1>%mask, <4 x float>%dst) 104 ret <4 x float> %res 105} 106 107; AVX2-LABEL: test8 108; AVX2: vpmaskmovd {{.*}}(%rdi) 109; AVX2: blend 110 111; SKX-LABEL: test8 112; SKX: vmovdqu32 (%rdi){{.*}}{%k1} 113define <4 x i32> @test8(<4 x i32> %trigger, <4 x i32>* %addr, <4 x i32> %dst) { 114 %mask = icmp eq <4 x i32> %trigger, zeroinitializer 115 %res = call <4 x i32> @llvm.masked.load.v4i32(<4 x i32>* %addr, i32 4, <4 x i1>%mask, <4 x i32>%dst) 116 ret <4 x i32> %res 117} 118 119; AVX2-LABEL: test9 120; AVX2: vpmaskmovd %xmm 121 122; SKX-LABEL: test9 123; SKX: vmovdqu32 %xmm{{.*}}{%k1} 124define void @test9(<4 x i32> %trigger, <4 x i32>* %addr, <4 x i32> %val) { 125 %mask = icmp eq <4 x i32> %trigger, zeroinitializer 126 call void @llvm.masked.store.v4i32(<4 x i32>%val, <4 x i32>* %addr, i32 4, <4 x i1>%mask) 127 ret void 128} 129 130; AVX2-LABEL: test10 131; AVX2: vmaskmovpd (%rdi), %ymm 132; AVX2: blend 133 134; SKX-LABEL: test10 135; SKX: vmovapd {{.*}}{%k1} 136define <4 x double> @test10(<4 x i32> %trigger, <4 x double>* %addr, <4 x double> %dst) { 137 %mask = icmp eq <4 x i32> %trigger, zeroinitializer 138 %res = call <4 x double> @llvm.masked.load.v4f64(<4 x double>* %addr, i32 32, <4 x i1>%mask, <4 x double>%dst) 139 ret <4 x double> %res 140} 141 142; AVX2-LABEL: test11 143; AVX2: vmaskmovps 144; AVX2: vblendvps 145 146; SKX-LABEL: test11 147; SKX: vmovaps {{.*}}{%k1} 148define <8 x float> @test11(<8 x i32> %trigger, <8 x float>* %addr, <8 x float> %dst) { 149 %mask = icmp eq <8 x i32> %trigger, zeroinitializer 150 %res = call <8 x float> @llvm.masked.load.v8f32(<8 x float>* %addr, i32 32, <8 x i1>%mask, <8 x float>%dst) 151 ret <8 x float> %res 152} 153 154; AVX2-LABEL: test12 155; AVX2: vpmaskmovd %ymm 156 157; SKX-LABEL: test12 158; SKX: vmovdqu32 {{.*}}{%k1} 159define void @test12(<8 x i32> %trigger, <8 x i32>* %addr, <8 x i32> %val) { 160 %mask = icmp eq <8 x i32> %trigger, zeroinitializer 161 call void @llvm.masked.store.v8i32(<8 x i32>%val, <8 x i32>* %addr, i32 4, <8 x i1>%mask) 162 ret void 163} 164 165; AVX512-LABEL: test13 166; AVX512: vmovups %zmm1, (%rdi) {%k1} 167 168define void @test13(<16 x i32> %trigger, <16 x float>* %addr, <16 x float> %val) { 169 %mask = icmp eq <16 x i32> %trigger, zeroinitializer 170 call void @llvm.masked.store.v16f32(<16 x float>%val, <16 x float>* %addr, i32 4, <16 x i1>%mask) 171 ret void 172} 173 174; AVX2-LABEL: test14 175; AVX2: vpshufd 176; AVX2: vmovq 177; AVX2: vmaskmovps 178 179; SKX-LABEL: test14 180; SKX: kshiftl 181; SKX: kshiftr 182; SKX: vmovups {{.*}}{%k1} 183 184define void @test14(<2 x i32> %trigger, <2 x float>* %addr, <2 x float> %val) { 185 %mask = icmp eq <2 x i32> %trigger, zeroinitializer 186 call void @llvm.masked.store.v2f32(<2 x float>%val, <2 x float>* %addr, i32 4, <2 x i1>%mask) 187 ret void 188} 189 190; AVX2-LABEL: test15 191; AVX2: vpmaskmovd 192 193; SKX-LABEL: test15 194; SKX: kshiftl 195; SKX: kshiftr 196; SKX: vmovdqu32 {{.*}}{%k1} 197define void @test15(<2 x i32> %trigger, <2 x i32>* %addr, <2 x i32> %val) { 198 %mask = icmp eq <2 x i32> %trigger, zeroinitializer 199 call void @llvm.masked.store.v2i32(<2 x i32>%val, <2 x i32>* %addr, i32 4, <2 x i1>%mask) 200 ret void 201} 202 203; AVX2-LABEL: test16 204; AVX2: vmaskmovps 205; AVX2: vblendvps 206 207; SKX-LABEL: test16 208; SKX: kshiftl 209; SKX: kshiftr 210; SKX: vmovups {{.*}}{%k1} 211define <2 x float> @test16(<2 x i32> %trigger, <2 x float>* %addr, <2 x float> %dst) { 212 %mask = icmp eq <2 x i32> %trigger, zeroinitializer 213 %res = call <2 x float> @llvm.masked.load.v2f32(<2 x float>* %addr, i32 4, <2 x i1>%mask, <2 x float>%dst) 214 ret <2 x float> %res 215} 216 217; AVX2-LABEL: test17 218; AVX2: vpmaskmovd 219; AVX2: vblendvps 220; AVX2: vpmovsxdq 221 222; SKX-LABEL: test17 223; SKX: kshiftl 224; SKX: kshiftr 225; SKX: vmovdqu32 {{.*}}{%k1} 226define <2 x i32> @test17(<2 x i32> %trigger, <2 x i32>* %addr, <2 x i32> %dst) { 227 %mask = icmp eq <2 x i32> %trigger, zeroinitializer 228 %res = call <2 x i32> @llvm.masked.load.v2i32(<2 x i32>* %addr, i32 4, <2 x i1>%mask, <2 x i32>%dst) 229 ret <2 x i32> %res 230} 231 232; AVX2-LABEL: test18 233; AVX2: vmaskmovps 234; AVX2-NOT: blend 235define <2 x float> @test18(<2 x i32> %trigger, <2 x float>* %addr) { 236 %mask = icmp eq <2 x i32> %trigger, zeroinitializer 237 %res = call <2 x float> @llvm.masked.load.v2f32(<2 x float>* %addr, i32 4, <2 x i1>%mask, <2 x float>undef) 238 ret <2 x float> %res 239} 240 241 242declare <16 x i32> @llvm.masked.load.v16i32(<16 x i32>*, i32, <16 x i1>, <16 x i32>) 243declare <4 x i32> @llvm.masked.load.v4i32(<4 x i32>*, i32, <4 x i1>, <4 x i32>) 244declare <2 x i32> @llvm.masked.load.v2i32(<2 x i32>*, i32, <2 x i1>, <2 x i32>) 245declare void @llvm.masked.store.v16i32(<16 x i32>, <16 x i32>*, i32, <16 x i1>) 246declare void @llvm.masked.store.v8i32(<8 x i32>, <8 x i32>*, i32, <8 x i1>) 247declare void @llvm.masked.store.v4i32(<4 x i32>, <4 x i32>*, i32, <4 x i1>) 248declare void @llvm.masked.store.v2f32(<2 x float>, <2 x float>*, i32, <2 x i1>) 249declare void @llvm.masked.store.v2i32(<2 x i32>, <2 x i32>*, i32, <2 x i1>) 250declare void @llvm.masked.store.v16f32(<16 x float>, <16 x float>*, i32, <16 x i1>) 251declare void @llvm.masked.store.v16f32p(<16 x float>*, <16 x float>**, i32, <16 x i1>) 252declare <16 x float> @llvm.masked.load.v16f32(<16 x float>*, i32, <16 x i1>, <16 x float>) 253declare <8 x float> @llvm.masked.load.v8f32(<8 x float>*, i32, <8 x i1>, <8 x float>) 254declare <4 x float> @llvm.masked.load.v4f32(<4 x float>*, i32, <4 x i1>, <4 x float>) 255declare <2 x float> @llvm.masked.load.v2f32(<2 x float>*, i32, <2 x i1>, <2 x float>) 256declare <8 x double> @llvm.masked.load.v8f64(<8 x double>*, i32, <8 x i1>, <8 x double>) 257declare <4 x double> @llvm.masked.load.v4f64(<4 x double>*, i32, <4 x i1>, <4 x double>) 258declare <2 x double> @llvm.masked.load.v2f64(<2 x double>*, i32, <2 x i1>, <2 x double>) 259declare void @llvm.masked.store.v8f64(<8 x double>, <8 x double>*, i32, <8 x i1>) 260declare void @llvm.masked.store.v2f64(<2 x double>, <2 x double>*, i32, <2 x i1>) 261declare void @llvm.masked.store.v2i64(<2 x i64>, <2 x i64>*, i32, <2 x i1>) 262 263