Home
last modified time | relevance | path

Searched refs:setReg (Results 1 – 25 of 59) sorted by relevance

123

/external/llvm/lib/Target/PowerPC/
DPPCVSXFMAMutate.cpp211 MI->getOperand(0).setReg(KilledProdReg); in processBlock()
212 MI->getOperand(1).setReg(KilledProdReg); in processBlock()
213 MI->getOperand(3).setReg(AddReg); in processBlock()
214 MI->getOperand(2).setReg(OtherProdReg); in processBlock()
248 UseMO.setReg(KilledProdReg); in processBlock()
DPPCVSXCopy.cpp116 SrcMO.setReg(NewVReg); in processBlock()
136 SrcMO.setReg(NewVReg); in processBlock()
/external/llvm/lib/Target/Hexagon/
DHexagonPeephole.cpp256 MI->getOperand(0).setReg(PeepholeSrc); in runOnMachineFunction()
286 MI->getOperand(PR).setReg(POrig); in runOnMachineFunction()
309 Dst.setReg(Src.getReg()); in ChangeOpInto()
/external/llvm/lib/Target/Sparc/
DDelaySlotFiller.cpp380 AddMI->getOperand(0).setReg(reg - SP::I0 + SP::O0); in combineRestoreADD()
419 OrMI->getOperand(0).setReg(reg - SP::I0 + SP::O0); in combineRestoreOR()
453 RestoreMI->getOperand(0).setReg(reg - SP::I0 + SP::O0); in combineRestoreSETHIi()
454 RestoreMI->getOperand(1).setReg(SP::G0); in combineRestoreSETHIi()
DSparcRegisterInfo.cpp188 MI.getOperand(2).setReg(SrcOddReg); in eliminateFrameIndex()
201 MI.getOperand(0).setReg(DestOddReg); in eliminateFrameIndex()
/external/llvm/lib/Target/SystemZ/
DSystemZShortenInst.cpp88 MI.getOperand(0).setReg(SystemZMC::getRegAsGR64(Reg)); in shortenIIF()
93 MI.getOperand(0).setReg(SystemZMC::getRegAsGR64(Reg)); in shortenIIF()
/external/llvm/lib/CodeGen/
DAntiDepBreaker.h61 MI->getOperand(0).setReg(NewReg); in UpdateDbgValue()
DPeepholeOptimizer.cpp452 UseMO->setReg(NewVR); in INITIALIZE_PASS_DEPENDENCY()
661 MOSrc.setReg(NewReg); in RewriteCurrentSource()
712 MO.setReg(NewReg); in RewriteCurrentSource()
761 CopyLike.getOperand(CurrentSrcIdx).setReg(NewReg); in RewriteCurrentSource()
842 MO.setReg(NewReg); in RewriteCurrentSource()
DTargetInstrInfo.cpp166 MI->getOperand(0).setReg(Reg0); in commuteInstruction()
169 MI->getOperand(Idx2).setReg(Reg1); in commuteInstruction()
170 MI->getOperand(Idx1).setReg(Reg2); in commuteInstruction()
230 MO.setReg(Pred[j].getReg()); in PredicateInstruction()
DTailDuplication.cpp444 MO.setReg(NewReg); in DuplicateInstruction()
451 MO.setReg(VI->second); in DuplicateInstruction()
517 II->getOperand(Idx).setReg(SrcReg); in UpdateSuccessorsPHIs()
529 II->getOperand(Idx).setReg(Reg); in UpdateSuccessorsPHIs()
DMachineRegisterInfo.cpp296 O.setReg(ToReg); in replaceRegWith()
441 UseMI->getOperand(0).setReg(0U); in markUsesInDebugValueAsUndef()
DRegAllocFast.cpp678 MO.setReg(PhysReg); in setPhysReg()
683 MO.setReg(PhysReg ? TRI->getSubReg(PhysReg, MO.getSubReg()) : 0); in setPhysReg()
866 MO.setReg(0); in AllocateBasicBlock()
/external/llvm/lib/Target/R600/
DSIPrepareScratchRegs.cpp192 MI.getOperand(2).setReg(ScratchRsrcReg); in runOnMachineFunction()
195 MI.getOperand(3).setReg(ScratchOffsetReg); in runOnMachineFunction()
DR600EmitClauseMarkers.cpp165 Consts[i].first->setReg( in SubstituteKCacheBank()
169 Consts[i].first->setReg( in SubstituteKCacheBank()
DR600InstrInfo.cpp984 MO2.setReg(AMDGPU::PRED_SEL_ONE); in ReverseBranchCondition()
987 MO2.setReg(AMDGPU::PRED_SEL_ZERO); in ReverseBranchCondition()
1021 .setReg(Pred[2].getReg()); in PredicateInstruction()
1023 .setReg(Pred[2].getReg()); in PredicateInstruction()
1025 .setReg(Pred[2].getReg()); in PredicateInstruction()
1027 .setReg(Pred[2].getReg()); in PredicateInstruction()
1035 PMO.setReg(Pred[2].getReg()); in PredicateInstruction()
1296 .setReg(MO.getReg()); in buildSlotOfVectorInstruction()
DR600ExpandSpecialInstrs.cpp88 DstOp.setReg(AMDGPU::OQAP); in runOnMachineFunction()
94 Mov->getOperand(MovPredSelIdx).setReg( in runOnMachineFunction()
/external/mesa3d/src/gallium/drivers/radeon/
DR600InstrInfo.cpp427 MO2.setReg(AMDGPU::PRED_SEL_ONE); in ReverseBranchCondition()
430 MO2.setReg(AMDGPU::PRED_SEL_ZERO); in ReverseBranchCondition()
462 PMO.setReg(Pred[2].getReg()); in PredicateInstruction()
DAMDILCFGStructurizer.cpp1696 RegiT setReg) { in mergeLoopbreakBlock() argument
1722 if (exitBlk == exitLandBlk && setReg == INVALIDREGNUM) { in mergeLoopbreakBlock()
1741 if (setReg != INVALIDREGNUM) { in mergeLoopbreakBlock()
1742 CFGTraits::insertAssignInstrBefore(branchInstrPos, passRep, setReg, 1); in mergeLoopbreakBlock()
1765 RegiT setReg) { in settleLoopcontBlock() argument
1792 (setReg == INVALIDREGNUM && (&*contingBlk->rbegin()) == branchInstr); in settleLoopcontBlock()
1802 if (setReg != INVALIDREGNUM) { in settleLoopcontBlock()
1803 CFGTraits::insertAssignInstrBefore(branchInstrPos, passRep, setReg, 1); in settleLoopcontBlock()
1826 if (setReg != INVALIDREGNUM) { in settleLoopcontBlock()
1827 CFGTraits::insertAssignInstrBefore(contingBlk, passRep, setReg, 1); in settleLoopcontBlock()
/external/llvm/lib/Target/Mips/
DMipsOptimizePICCall.cpp138 I->getOperand(0).setReg(DstReg); in setCallTargetReg()
229 getCallTargetRegOpnd(*I)->setReg(getReg(Entry)); in visitNode()
DMipsFastISel.cpp49 void setReg(unsigned Reg) { in setReg() function in __anon53f8ae240111::MipsFastISel::Address
437 Addr.setReg(getRegForValue(Obj)); in computeAddress()
1059 Addr.setReg(Mips::SP); in processCallArgs()
1448 Addr.setReg(DestReg); in simplifyAddress()
/external/llvm/lib/Target/AArch64/
DAArch64DeadRegisterDefinitionsPass.cpp111 MO.setReg(NewReg); in processMachineBasicBlock()
DAArch64A57FPLoadBalancing.cpp561 U.setReg(Substs[OrigReg]); in colorChain()
587 MO.setReg(Reg); in colorChain()
/external/llvm/include/llvm/MC/
DMCInst.h69 void setReg(unsigned Reg) { in setReg() function
/external/libcxxabi/src/Unwind/
DUnwindCursor.hpp379 virtual void setReg(int, unw_word_t) { in setReg() function in libunwind::AbstractUnwindCursor
424 virtual void setReg(int, unw_word_t);
585 void UnwindCursor<A, R>::setReg(int regNum, unw_word_t value) { in setReg() function in libunwind::UnwindCursor
1297 setReg(UNW_REG_SP, getReg(UNW_REG_SP) + _info.gp); in step()
Dlibunwind.cpp180 co->setReg(regNum, (pint_t)value); in unw_set_reg()

123