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Searched refs:reg8 (Results 1 – 24 of 24) sorted by relevance

/external/libvpx/libvpx/vpx_dsp/mips/
Didct16x16_msa.c15 v8i16 reg0, reg2, reg4, reg6, reg8, reg10, reg12, reg14; in vpx_idct16_1d_rows_msa() local
21 LD_SH8(input, 16, reg8, reg9, reg10, reg11, reg12, reg13, reg14, reg15); in vpx_idct16_1d_rows_msa()
25 TRANSPOSE8x8_SH_SH(reg8, reg9, reg10, reg11, reg12, reg13, reg14, reg15, in vpx_idct16_1d_rows_msa()
26 reg8, reg9, reg10, reg11, reg12, reg13, reg14, reg15); in vpx_idct16_1d_rows_msa()
31 DOTP_CONST_PAIR(reg0, reg8, cospi_16_64, cospi_16_64, reg0, reg8); in vpx_idct16_1d_rows_msa()
33 BUTTERFLY_4(reg8, reg0, reg4, reg12, reg2, reg6, reg10, reg14); in vpx_idct16_1d_rows_msa()
35 reg8); in vpx_idct16_1d_rows_msa()
80 BUTTERFLY_4(reg8, reg10, reg11, reg5, loc0, reg4, reg9, loc1); in vpx_idct16_1d_rows_msa()
86 BUTTERFLY_4(reg12, reg14, reg13, reg3, reg8, reg6, reg7, reg5); in vpx_idct16_1d_rows_msa()
96 TRANSPOSE8x8_SH_SH(reg0, reg2, reg4, reg6, reg8, reg10, reg12, reg14, in vpx_idct16_1d_rows_msa()
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/external/llvm/test/DebugInfo/
Ddwarfdump-debug-frame-simple.test10 ; FRAMES-NEXT: DW_CFA_offset: reg8 -4
/external/elfutils/src/tests/
Drun-addrcfi.sh30 return address in reg8
40 integer reg8 (%eip): location expression: call_frame_cfa plus_uconst(-4)
77 return address in reg8
87 integer reg8 (%eip): location expression: call_frame_cfa plus_uconst(-4)
139 integer reg8 (%r8): undefined
205 integer reg8 (%r8): undefined
309 integer reg8 (r8): undefined
1336 integer reg8 (r8): undefined
2362 integer reg8 (%r8): same_value
2439 integer reg8 (%r8): same_value
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/external/lldb/tools/debugserver/source/MacOSX/i386/
DDNBArchImplI386.cpp1015 #define DEFINE_GPR_PSEUDO_8H(reg8,reg32) { e_regSetGPR, gpr_##reg8 , #reg8 , NULL, Uint, Hex, 1, G… argument
1016 #define DEFINE_GPR_PSEUDO_8L(reg8,reg32) { e_regSetGPR, gpr_##reg8 , #reg8 , NULL, Uint, Hex, 1, G… argument
/external/lldb/tools/debugserver/source/MacOSX/x86_64/
DDNBArchImplX86_64.cpp1286 #define DEFINE_GPR_PSEUDO_8H(reg8,reg64) { e_regSetGPR, gpr_##reg8 , #reg8 , NULL, Uint, Hex, 1, G… argument
1287 #define DEFINE_GPR_PSEUDO_8L(reg8,reg64) { e_regSetGPR, gpr_##reg8 , #reg8 , NULL, Uint, Hex, 1, G… argument
/external/llvm/test/CodeGen/R600/
Dbig_alu.ll6 …eg5, <4 x float> inreg %reg6, <4 x float> inreg %reg7, <4 x float> inreg %reg8, <4 x float> inreg …
14 %6 = extractelement <4 x float> %reg8, i32 0
19 %11 = extractelement <4 x float> %reg8, i32 0
24 %16 = extractelement <4 x float> %reg8, i32 0
29 %21 = extractelement <4 x float> %reg8, i32 0
/external/v8/src/arm64/
Dassembler-arm64.cc222 const CPURegister& reg7, const CPURegister& reg8) { in AreAliased() argument
229 const CPURegister regs[] = {reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8}; in AreAliased()
259 const CPURegister& reg7, const CPURegister& reg8) { in AreSameSizeAndType() argument
268 match &= !reg8.IsValid() || reg8.IsSameSizeAndType(reg1); in AreSameSizeAndType()
Dassembler-arm64.h425 const CPURegister& reg8 = NoReg);
438 const CPURegister& reg8 = NoCPUReg);
/external/llvm/include/llvm/Support/
DDwarf.def203 HANDLE_DW_OP(0x58, reg8)
/external/v8/src/x87/
Dmacro-assembler-x87.cc2977 Register reg8) { in AreAliased() argument
2980 reg7.is_valid() + reg8.is_valid(); in AreAliased()
2990 if (reg8.is_valid()) regs |= reg8.bit(); in AreAliased()
Dmacro-assembler-x87.h42 Register reg8 = no_reg);
/external/v8/src/ia32/
Dmacro-assembler-ia32.cc3017 Register reg8) { in AreAliased() argument
3020 reg7.is_valid() + reg8.is_valid(); in AreAliased()
3030 if (reg8.is_valid()) regs |= reg8.bit(); in AreAliased()
Dmacro-assembler-ia32.h42 Register reg8 = no_reg);
/external/elfutils/src/libdw/
Dknown-dwarf.h525 ONE_KNOWN_DW_OP_DESC (reg8, DW_OP_reg8, "Register 8.") \
/external/v8/src/arm/
Dmacro-assembler-arm.cc4003 Register reg8) { in AreAliased() argument
4006 reg7.is_valid() + reg8.is_valid(); in AreAliased()
4016 if (reg8.is_valid()) regs |= reg8.bit(); in AreAliased()
Dmacro-assembler-arm.h64 Register reg8 = no_reg);
/external/vixl/src/vixl/a64/
Dassembler-a64.cc5365 const CPURegister& reg7, const CPURegister& reg8) { in AreAliased() argument
5372 const CPURegister regs[] = {reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8}; in AreAliased()
5400 const CPURegister& reg7, const CPURegister& reg8) { in AreSameSizeAndType() argument
5409 match &= !reg8.IsValid() || reg8.IsSameSizeAndType(reg1); in AreSameSizeAndType()
Dassembler-a64.h414 const CPURegister& reg8 = NoReg);
428 const CPURegister& reg8 = NoCPUReg);
/external/v8/src/x64/
Dmacro-assembler-x64.h62 Register reg8 = no_reg);
Dmacro-assembler-x64.cc4991 Register reg8) { in AreAliased() argument
4994 reg7.is_valid() + reg8.is_valid(); in AreAliased()
5004 if (reg8.is_valid()) regs |= reg8.bit(); in AreAliased()
/external/v8/src/mips64/
Dmacro-assembler-mips64.cc5987 Register reg8) { in AreAliased() argument
5990 reg7.is_valid() + reg8.is_valid(); in AreAliased()
6000 if (reg8.is_valid()) regs |= reg8.bit(); in AreAliased()
Dmacro-assembler-mips64.h100 Register reg8 = no_reg);
/external/v8/src/mips/
Dmacro-assembler-mips.cc6002 Register reg8) { in AreAliased() argument
6005 reg7.is_valid() + reg8.is_valid(); in AreAliased()
6015 if (reg8.is_valid()) regs |= reg8.bit(); in AreAliased()
Dmacro-assembler-mips.h94 Register reg8 = no_reg);