1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef _UAPI_EXYNOS_DRM_H_ 20 #define _UAPI_EXYNOS_DRM_H_ 21 #include <drm/drm.h> 22 struct drm_exynos_gem_create { 23 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 24 uint64_t size; 25 unsigned int flags; 26 unsigned int handle; 27 }; 28 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 29 struct drm_exynos_gem_info { 30 unsigned int handle; 31 unsigned int flags; 32 uint64_t size; 33 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 34 }; 35 struct drm_exynos_vidi_connection { 36 unsigned int connection; 37 unsigned int extensions; 38 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 39 uint64_t edid; 40 }; 41 enum e_drm_exynos_gem_mem_type { 42 EXYNOS_BO_CONTIG = 0 << 0, 43 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 44 EXYNOS_BO_NONCONTIG = 1 << 0, 45 EXYNOS_BO_NONCACHABLE = 0 << 1, 46 EXYNOS_BO_CACHABLE = 1 << 1, 47 EXYNOS_BO_WC = 1 << 2, 48 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 49 EXYNOS_BO_MASK = EXYNOS_BO_NONCONTIG | EXYNOS_BO_CACHABLE | EXYNOS_BO_WC 50 }; 51 struct drm_exynos_g2d_get_ver { 52 __u32 major; 53 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 54 __u32 minor; 55 }; 56 struct drm_exynos_g2d_cmd { 57 __u32 offset; 58 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 59 __u32 data; 60 }; 61 enum drm_exynos_g2d_buf_type { 62 G2D_BUF_USERPTR = 1 << 31, 63 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 64 }; 65 enum drm_exynos_g2d_event_type { 66 G2D_EVENT_NOT, 67 G2D_EVENT_NONSTOP, 68 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 69 G2D_EVENT_STOP, 70 }; 71 struct drm_exynos_g2d_userptr { 72 unsigned long userptr; 73 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 74 unsigned long size; 75 }; 76 struct drm_exynos_g2d_set_cmdlist { 77 __u64 cmd; 78 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 79 __u64 cmd_buf; 80 __u32 cmd_nr; 81 __u32 cmd_buf_nr; 82 __u64 event_type; 83 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 84 __u64 user_data; 85 }; 86 struct drm_exynos_g2d_exec { 87 __u64 async; 88 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 89 }; 90 enum drm_exynos_ops_id { 91 EXYNOS_DRM_OPS_SRC, 92 EXYNOS_DRM_OPS_DST, 93 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 94 EXYNOS_DRM_OPS_MAX, 95 }; 96 struct drm_exynos_sz { 97 __u32 hsize; 98 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 99 __u32 vsize; 100 }; 101 struct drm_exynos_pos { 102 __u32 x; 103 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 104 __u32 y; 105 __u32 w; 106 __u32 h; 107 }; 108 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 109 enum drm_exynos_flip { 110 EXYNOS_DRM_FLIP_NONE = (0 << 0), 111 EXYNOS_DRM_FLIP_VERTICAL = (1 << 0), 112 EXYNOS_DRM_FLIP_HORIZONTAL = (1 << 1), 113 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 114 EXYNOS_DRM_FLIP_BOTH = EXYNOS_DRM_FLIP_VERTICAL | EXYNOS_DRM_FLIP_HORIZONTAL, 115 }; 116 enum drm_exynos_degree { 117 EXYNOS_DRM_DEGREE_0, 118 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 119 EXYNOS_DRM_DEGREE_90, 120 EXYNOS_DRM_DEGREE_180, 121 EXYNOS_DRM_DEGREE_270, 122 }; 123 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 124 enum drm_exynos_planer { 125 EXYNOS_DRM_PLANAR_Y, 126 EXYNOS_DRM_PLANAR_CB, 127 EXYNOS_DRM_PLANAR_CR, 128 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 129 EXYNOS_DRM_PLANAR_MAX, 130 }; 131 struct drm_exynos_ipp_prop_list { 132 __u32 version; 133 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 134 __u32 ipp_id; 135 __u32 count; 136 __u32 writeback; 137 __u32 flip; 138 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 139 __u32 degree; 140 __u32 csc; 141 __u32 crop; 142 __u32 scale; 143 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 144 __u32 refresh_min; 145 __u32 refresh_max; 146 __u32 reserved; 147 struct drm_exynos_sz crop_min; 148 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 149 struct drm_exynos_sz crop_max; 150 struct drm_exynos_sz scale_min; 151 struct drm_exynos_sz scale_max; 152 }; 153 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 154 struct drm_exynos_ipp_config { 155 enum drm_exynos_ops_id ops_id; 156 enum drm_exynos_flip flip; 157 enum drm_exynos_degree degree; 158 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 159 __u32 fmt; 160 struct drm_exynos_sz sz; 161 struct drm_exynos_pos pos; 162 }; 163 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 164 enum drm_exynos_ipp_cmd { 165 IPP_CMD_NONE, 166 IPP_CMD_M2M, 167 IPP_CMD_WB, 168 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 169 IPP_CMD_OUTPUT, 170 IPP_CMD_MAX, 171 }; 172 struct drm_exynos_ipp_property { 173 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 174 struct drm_exynos_ipp_config config[EXYNOS_DRM_OPS_MAX]; 175 enum drm_exynos_ipp_cmd cmd; 176 __u32 ipp_id; 177 __u32 prop_id; 178 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 179 __u32 refresh_rate; 180 }; 181 enum drm_exynos_ipp_buf_type { 182 IPP_BUF_ENQUEUE, 183 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 184 IPP_BUF_DEQUEUE, 185 }; 186 struct drm_exynos_ipp_queue_buf { 187 enum drm_exynos_ops_id ops_id; 188 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 189 enum drm_exynos_ipp_buf_type buf_type; 190 __u32 prop_id; 191 __u32 buf_id; 192 __u32 handle[EXYNOS_DRM_PLANAR_MAX]; 193 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 194 __u32 reserved; 195 __u64 user_data; 196 }; 197 enum drm_exynos_ipp_ctrl { 198 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 199 IPP_CTRL_PLAY, 200 IPP_CTRL_STOP, 201 IPP_CTRL_PAUSE, 202 IPP_CTRL_RESUME, 203 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 204 IPP_CTRL_MAX, 205 }; 206 struct drm_exynos_ipp_cmd_ctrl { 207 __u32 prop_id; 208 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 209 enum drm_exynos_ipp_ctrl ctrl; 210 }; 211 #define DRM_EXYNOS_GEM_CREATE 0x00 212 #define DRM_EXYNOS_GEM_GET 0x04 213 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 214 #define DRM_EXYNOS_VIDI_CONNECTION 0x07 215 #define DRM_EXYNOS_G2D_GET_VER 0x20 216 #define DRM_EXYNOS_G2D_SET_CMDLIST 0x21 217 #define DRM_EXYNOS_G2D_EXEC 0x22 218 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 219 #define DRM_EXYNOS_IPP_GET_PROPERTY 0x30 220 #define DRM_EXYNOS_IPP_SET_PROPERTY 0x31 221 #define DRM_EXYNOS_IPP_QUEUE_BUF 0x32 222 #define DRM_EXYNOS_IPP_CMD_CTRL 0x33 223 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 224 #define DRM_IOCTL_EXYNOS_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_GEM_CREATE, struct drm_exynos_gem_create) 225 #define DRM_IOCTL_EXYNOS_GEM_GET DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_GEM_GET, struct drm_exynos_gem_info) 226 #define DRM_IOCTL_EXYNOS_VIDI_CONNECTION DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_VIDI_CONNECTION, struct drm_exynos_vidi_connection) 227 #define DRM_IOCTL_EXYNOS_G2D_GET_VER DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_G2D_GET_VER, struct drm_exynos_g2d_get_ver) 228 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 229 #define DRM_IOCTL_EXYNOS_G2D_SET_CMDLIST DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_G2D_SET_CMDLIST, struct drm_exynos_g2d_set_cmdlist) 230 #define DRM_IOCTL_EXYNOS_G2D_EXEC DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_G2D_EXEC, struct drm_exynos_g2d_exec) 231 #define DRM_IOCTL_EXYNOS_IPP_GET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_IPP_GET_PROPERTY, struct drm_exynos_ipp_prop_list) 232 #define DRM_IOCTL_EXYNOS_IPP_SET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_IPP_SET_PROPERTY, struct drm_exynos_ipp_property) 233 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 234 #define DRM_IOCTL_EXYNOS_IPP_QUEUE_BUF DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_IPP_QUEUE_BUF, struct drm_exynos_ipp_queue_buf) 235 #define DRM_IOCTL_EXYNOS_IPP_CMD_CTRL DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_IPP_CMD_CTRL, struct drm_exynos_ipp_cmd_ctrl) 236 #define DRM_EXYNOS_G2D_EVENT 0x80000000 237 #define DRM_EXYNOS_IPP_EVENT 0x80000001 238 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 239 struct drm_exynos_g2d_event { 240 struct drm_event base; 241 __u64 user_data; 242 __u32 tv_sec; 243 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 244 __u32 tv_usec; 245 __u32 cmdlist_no; 246 __u32 reserved; 247 }; 248 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 249 struct drm_exynos_ipp_event { 250 struct drm_event base; 251 __u64 user_data; 252 __u32 tv_sec; 253 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 254 __u32 tv_usec; 255 __u32 prop_id; 256 __u32 reserved; 257 __u32 buf_id[EXYNOS_DRM_OPS_MAX]; 258 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 259 }; 260 #endif 261