1============================ 2User Guide for R600 Back-end 3============================ 4 5Introduction 6============ 7 8The R600 back-end provides ISA code generation for AMD GPUs, starting with 9the R600 family up until the current Volcanic Islands (GCN Gen 3). 10 11 12Assembler 13========= 14 15The assembler is currently considered experimental. 16 17For syntax examples look in test/MC/R600. 18 19Below some of the currently supported features (modulo bugs). These 20all apply to the Southern Islands ISA, Sea Islands and Volcanic Islands 21are also supported but may be missing some instructions and have more bugs: 22 23DS Instructions 24--------------- 25All DS instructions are supported. 26 27MUBUF Instructions 28------------------ 29All non-atomic MUBUF instructions are supported. 30 31SMRD Instructions 32----------------- 33Only the s_load_dword* SMRD instructions are supported. 34 35SOP1 Instructions 36----------------- 37All SOP1 instructions are supported. 38 39SOP2 Instructions 40----------------- 41All SOP2 instructions are supported. 42 43SOPC Instructions 44----------------- 45All SOPC instructions are supported. 46 47SOPP Instructions 48----------------- 49 50Unless otherwise mentioned, all SOPP instructions that have one or more 51operands accept integer operands only. No verification is performed 52on the operands, so it is up to the programmer to be familiar with the 53range or acceptable values. 54 55s_waitcnt 56^^^^^^^^^ 57 58s_waitcnt accepts named arguments to specify which memory counter(s) to 59wait for. 60 61.. code-block:: nasm 62 63 // Wait for all counters to be 0 64 s_waitcnt 0 65 66 // Equivalent to s_waitcnt 0. Counter names can also be delimited by 67 // '&' or ','. 68 s_waitcnt vmcnt(0) expcnt(0) lgkcmt(0) 69 70 // Wait for vmcnt counter to be 1. 71 s_waitcnt vmcnt(1) 72 73VOP1, VOP2, VOP3, VOPC Instructions 74----------------------------------- 75 76All 32-bit and 64-bit encodings should work. 77 78The assembler will automatically detect which encoding size to use for 79VOP1, VOP2, and VOPC instructions based on the operands. If you want to force 80a specific encoding size, you can add an _e32 (for 32-bit encoding) or 81_e64 (for 64-bit encoding) suffix to the instruction. Most, but not all 82instructions support an explicit suffix. These are all valid assembly 83strings: 84 85.. code-block:: nasm 86 87 v_mul_i32_i24 v1, v2, v3 88 v_mul_i32_i24_e32 v1, v2, v3 89 v_mul_i32_i24_e64 v1, v2, v3 90