1 //===-- MipsMCCodeEmitter.h - Convert Mips Code to Machine Code -----------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the MipsMCCodeEmitter class. 11 // 12 //===----------------------------------------------------------------------===// 13 // 14 15 #ifndef LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSMCCODEEMITTER_H 16 #define LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSMCCODEEMITTER_H 17 18 #include "llvm/MC/MCCodeEmitter.h" 19 #include "llvm/Support/DataTypes.h" 20 21 using namespace llvm; 22 23 namespace llvm { 24 class MCContext; 25 class MCExpr; 26 class MCInst; 27 class MCInstrInfo; 28 class MCFixup; 29 class MCOperand; 30 class MCSubtargetInfo; 31 class raw_ostream; 32 33 class MipsMCCodeEmitter : public MCCodeEmitter { 34 MipsMCCodeEmitter(const MipsMCCodeEmitter &) = delete; 35 void operator=(const MipsMCCodeEmitter &) = delete; 36 const MCInstrInfo &MCII; 37 MCContext &Ctx; 38 bool IsLittleEndian; 39 40 bool isMicroMips(const MCSubtargetInfo &STI) const; 41 42 public: MipsMCCodeEmitter(const MCInstrInfo & mcii,MCContext & Ctx_,bool IsLittle)43 MipsMCCodeEmitter(const MCInstrInfo &mcii, MCContext &Ctx_, bool IsLittle) 44 : MCII(mcii), Ctx(Ctx_), IsLittleEndian(IsLittle) {} 45 ~MipsMCCodeEmitter()46 ~MipsMCCodeEmitter() override {} 47 48 void EmitByte(unsigned char C, raw_ostream &OS) const; 49 50 void EmitInstruction(uint64_t Val, unsigned Size, const MCSubtargetInfo &STI, 51 raw_ostream &OS) const; 52 53 void EncodeInstruction(const MCInst &MI, raw_ostream &OS, 54 SmallVectorImpl<MCFixup> &Fixups, 55 const MCSubtargetInfo &STI) const override; 56 57 // getBinaryCodeForInstr - TableGen'erated function for getting the 58 // binary encoding for an instruction. 59 uint64_t getBinaryCodeForInstr(const MCInst &MI, 60 SmallVectorImpl<MCFixup> &Fixups, 61 const MCSubtargetInfo &STI) const; 62 63 // getJumpTargetOpValue - Return binary encoding of the jump 64 // target operand. If the machine operand requires relocation, 65 // record the relocation and return zero. 66 unsigned getJumpTargetOpValue(const MCInst &MI, unsigned OpNo, 67 SmallVectorImpl<MCFixup> &Fixups, 68 const MCSubtargetInfo &STI) const; 69 70 // getBranchJumpOpValueMM - Return binary encoding of the microMIPS jump 71 // target operand. If the machine operand requires relocation, 72 // record the relocation and return zero. 73 unsigned getJumpTargetOpValueMM(const MCInst &MI, unsigned OpNo, 74 SmallVectorImpl<MCFixup> &Fixups, 75 const MCSubtargetInfo &STI) const; 76 77 // getUImm5Lsl2Encoding - Return binary encoding of the microMIPS jump 78 // target operand. 79 unsigned getUImm5Lsl2Encoding(const MCInst &MI, unsigned OpNo, 80 SmallVectorImpl<MCFixup> &Fixups, 81 const MCSubtargetInfo &STI) const; 82 83 unsigned getSImm3Lsa2Value(const MCInst &MI, unsigned OpNo, 84 SmallVectorImpl<MCFixup> &Fixups, 85 const MCSubtargetInfo &STI) const; 86 87 unsigned getUImm6Lsl2Encoding(const MCInst &MI, unsigned OpNo, 88 SmallVectorImpl<MCFixup> &Fixups, 89 const MCSubtargetInfo &STI) const; 90 91 // getSImm9AddiuspValue - Return binary encoding of the microMIPS addiusp 92 // instruction immediate operand. 93 unsigned getSImm9AddiuspValue(const MCInst &MI, unsigned OpNo, 94 SmallVectorImpl<MCFixup> &Fixups, 95 const MCSubtargetInfo &STI) const; 96 97 // getBranchTargetOpValue - Return binary encoding of the branch 98 // target operand. If the machine operand requires relocation, 99 // record the relocation and return zero. 100 unsigned getBranchTargetOpValue(const MCInst &MI, unsigned OpNo, 101 SmallVectorImpl<MCFixup> &Fixups, 102 const MCSubtargetInfo &STI) const; 103 104 // getBranchTarget7OpValue - Return binary encoding of the microMIPS branch 105 // target operand. If the machine operand requires relocation, 106 // record the relocation and return zero. 107 unsigned getBranchTarget7OpValueMM(const MCInst &MI, unsigned OpNo, 108 SmallVectorImpl<MCFixup> &Fixups, 109 const MCSubtargetInfo &STI) const; 110 111 // getBranchTargetOpValueMMPC10 - Return binary encoding of the microMIPS 112 // 10-bit branch target operand. If the machine operand requires relocation, 113 // record the relocation and return zero. 114 unsigned getBranchTargetOpValueMMPC10(const MCInst &MI, unsigned OpNo, 115 SmallVectorImpl<MCFixup> &Fixups, 116 const MCSubtargetInfo &STI) const; 117 118 // getBranchTargetOpValue - Return binary encoding of the microMIPS branch 119 // target operand. If the machine operand requires relocation, 120 // record the relocation and return zero. 121 unsigned getBranchTargetOpValueMM(const MCInst &MI, unsigned OpNo, 122 SmallVectorImpl<MCFixup> &Fixups, 123 const MCSubtargetInfo &STI) const; 124 125 // getBranchTarget21OpValue - Return binary encoding of the branch 126 // offset operand. If the machine operand requires relocation, 127 // record the relocation and return zero. 128 unsigned getBranchTarget21OpValue(const MCInst &MI, unsigned OpNo, 129 SmallVectorImpl<MCFixup> &Fixups, 130 const MCSubtargetInfo &STI) const; 131 132 // getBranchTarget26OpValue - Return binary encoding of the branch 133 // offset operand. If the machine operand requires relocation, 134 // record the relocation and return zero. 135 unsigned getBranchTarget26OpValue(const MCInst &MI, unsigned OpNo, 136 SmallVectorImpl<MCFixup> &Fixups, 137 const MCSubtargetInfo &STI) const; 138 139 // getJumpOffset16OpValue - Return binary encoding of the jump 140 // offset operand. If the machine operand requires relocation, 141 // record the relocation and return zero. 142 unsigned getJumpOffset16OpValue(const MCInst &MI, unsigned OpNo, 143 SmallVectorImpl<MCFixup> &Fixups, 144 const MCSubtargetInfo &STI) const; 145 146 // getMachineOpValue - Return binary encoding of operand. If the machin 147 // operand requires relocation, record the relocation and return zero. 148 unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO, 149 SmallVectorImpl<MCFixup> &Fixups, 150 const MCSubtargetInfo &STI) const; 151 152 unsigned getMSAMemEncoding(const MCInst &MI, unsigned OpNo, 153 SmallVectorImpl<MCFixup> &Fixups, 154 const MCSubtargetInfo &STI) const; 155 156 unsigned getMemEncoding(const MCInst &MI, unsigned OpNo, 157 SmallVectorImpl<MCFixup> &Fixups, 158 const MCSubtargetInfo &STI) const; 159 unsigned getMemEncodingMMImm4(const MCInst &MI, unsigned OpNo, 160 SmallVectorImpl<MCFixup> &Fixups, 161 const MCSubtargetInfo &STI) const; 162 unsigned getMemEncodingMMImm4Lsl1(const MCInst &MI, unsigned OpNo, 163 SmallVectorImpl<MCFixup> &Fixups, 164 const MCSubtargetInfo &STI) const; 165 unsigned getMemEncodingMMImm4Lsl2(const MCInst &MI, unsigned OpNo, 166 SmallVectorImpl<MCFixup> &Fixups, 167 const MCSubtargetInfo &STI) const; 168 unsigned getMemEncodingMMSPImm5Lsl2(const MCInst &MI, unsigned OpNo, 169 SmallVectorImpl<MCFixup> &Fixups, 170 const MCSubtargetInfo &STI) const; 171 unsigned getMemEncodingMMGPImm7Lsl2(const MCInst &MI, unsigned OpNo, 172 SmallVectorImpl<MCFixup> &Fixups, 173 const MCSubtargetInfo &STI) const; 174 unsigned getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo, 175 SmallVectorImpl<MCFixup> &Fixups, 176 const MCSubtargetInfo &STI) const; 177 unsigned getMemEncodingMMImm4sp(const MCInst &MI, unsigned OpNo, 178 SmallVectorImpl<MCFixup> &Fixups, 179 const MCSubtargetInfo &STI) const; 180 unsigned getSizeExtEncoding(const MCInst &MI, unsigned OpNo, 181 SmallVectorImpl<MCFixup> &Fixups, 182 const MCSubtargetInfo &STI) const; 183 unsigned getSizeInsEncoding(const MCInst &MI, unsigned OpNo, 184 SmallVectorImpl<MCFixup> &Fixups, 185 const MCSubtargetInfo &STI) const; 186 187 // getLSAImmEncoding - Return binary encoding of LSA immediate. 188 unsigned getLSAImmEncoding(const MCInst &MI, unsigned OpNo, 189 SmallVectorImpl<MCFixup> &Fixups, 190 const MCSubtargetInfo &STI) const; 191 192 unsigned getSimm19Lsl2Encoding(const MCInst &MI, unsigned OpNo, 193 SmallVectorImpl<MCFixup> &Fixups, 194 const MCSubtargetInfo &STI) const; 195 196 unsigned getSimm18Lsl3Encoding(const MCInst &MI, unsigned OpNo, 197 SmallVectorImpl<MCFixup> &Fixups, 198 const MCSubtargetInfo &STI) const; 199 200 unsigned getUImm3Mod8Encoding(const MCInst &MI, unsigned OpNo, 201 SmallVectorImpl<MCFixup> &Fixups, 202 const MCSubtargetInfo &STI) const; 203 unsigned getUImm4AndValue(const MCInst &MI, unsigned OpNo, 204 SmallVectorImpl<MCFixup> &Fixups, 205 const MCSubtargetInfo &STI) const; 206 207 unsigned getRegisterPairOpValue(const MCInst &MI, unsigned OpNo, 208 SmallVectorImpl<MCFixup> &Fixups, 209 const MCSubtargetInfo &STI) const; 210 211 unsigned getMovePRegPairOpValue(const MCInst &MI, unsigned OpNo, 212 SmallVectorImpl<MCFixup> &Fixups, 213 const MCSubtargetInfo &STI) const; 214 215 unsigned getSimm23Lsl2Encoding(const MCInst &MI, unsigned OpNo, 216 SmallVectorImpl<MCFixup> &Fixups, 217 const MCSubtargetInfo &STI) const; 218 219 unsigned getExprOpValue(const MCExpr *Expr, SmallVectorImpl<MCFixup> &Fixups, 220 const MCSubtargetInfo &STI) const; 221 222 unsigned getRegisterListOpValue(const MCInst &MI, unsigned OpNo, 223 SmallVectorImpl<MCFixup> &Fixups, 224 const MCSubtargetInfo &STI) const; 225 226 unsigned getRegisterListOpValue16(const MCInst &MI, unsigned OpNo, 227 SmallVectorImpl<MCFixup> &Fixups, 228 const MCSubtargetInfo &STI) const; 229 }; // class MipsMCCodeEmitter 230 } // namespace llvm. 231 232 #endif 233