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1def addrimm12 : ComplexPattern<iPTR, 2, "selectIntAddrMM", [frameindex]>;
2def addrimm4lsl2 : ComplexPattern<iPTR, 2, "selectIntAddrLSL2MM", [frameindex]>;
3
4def simm4 : Operand<i32> {
5  let DecoderMethod = "DecodeSimm4";
6}
7def simm7 : Operand<i32>;
8def li_simm7 : Operand<i32> {
9  let DecoderMethod = "DecodeLiSimm7";
10}
11
12def simm12 : Operand<i32> {
13  let DecoderMethod = "DecodeSimm12";
14}
15
16def uimm5_lsl2 : Operand<OtherVT> {
17  let EncoderMethod = "getUImm5Lsl2Encoding";
18  let DecoderMethod = "DecodeUImm5lsl2";
19}
20
21def uimm6_lsl2 : Operand<i32> {
22  let EncoderMethod = "getUImm6Lsl2Encoding";
23  let DecoderMethod = "DecodeUImm6Lsl2";
24}
25
26def simm9_addiusp : Operand<i32> {
27  let EncoderMethod = "getSImm9AddiuspValue";
28  let DecoderMethod = "DecodeSimm9SP";
29}
30
31def uimm3_shift : Operand<i32> {
32  let EncoderMethod = "getUImm3Mod8Encoding";
33}
34
35def simm3_lsa2 : Operand<i32> {
36  let EncoderMethod = "getSImm3Lsa2Value";
37  let DecoderMethod = "DecodeAddiur2Simm7";
38}
39
40def uimm4_andi : Operand<i32> {
41  let EncoderMethod = "getUImm4AndValue";
42  let DecoderMethod = "DecodeANDI16Imm";
43}
44
45def immSExtAddiur2 : ImmLeaf<i32, [{return Imm == 1 || Imm == -1 ||
46                                           ((Imm % 4 == 0) &&
47                                            Imm < 28 && Imm > 0);}]>;
48
49def immSExtAddius5 : ImmLeaf<i32, [{return Imm >= -8 && Imm <= 7;}]>;
50
51def immZExtAndi16 : ImmLeaf<i32,
52  [{return (Imm == 128 || (Imm >= 1 && Imm <= 4) || Imm == 7 || Imm == 8 ||
53            Imm == 15 || Imm == 16 || Imm == 31 || Imm == 32 || Imm == 63 ||
54            Imm == 64 || Imm == 255 || Imm == 32768 || Imm == 65535 );}]>;
55
56def immZExt2Shift : ImmLeaf<i32, [{return Imm >= 1 && Imm <= 8;}]>;
57
58def immLi16 : ImmLeaf<i32, [{return Imm >= -1 && Imm <= 126;}]>;
59
60def MicroMipsMemGPRMM16AsmOperand : AsmOperandClass {
61  let Name = "MicroMipsMem";
62  let RenderMethod = "addMicroMipsMemOperands";
63  let ParserMethod = "parseMemOperand";
64  let PredicateMethod = "isMemWithGRPMM16Base";
65}
66
67class mem_mm_4_generic : Operand<i32> {
68  let PrintMethod = "printMemOperand";
69  let MIOperandInfo = (ops GPRMM16, simm4);
70  let OperandType = "OPERAND_MEMORY";
71  let ParserMatchClass = MicroMipsMemGPRMM16AsmOperand;
72}
73
74def mem_mm_4 : mem_mm_4_generic {
75  let EncoderMethod = "getMemEncodingMMImm4";
76}
77
78def mem_mm_4_lsl1 : mem_mm_4_generic {
79  let EncoderMethod = "getMemEncodingMMImm4Lsl1";
80}
81
82def mem_mm_4_lsl2 : mem_mm_4_generic {
83  let EncoderMethod = "getMemEncodingMMImm4Lsl2";
84}
85
86def MicroMipsMemSPAsmOperand : AsmOperandClass {
87  let Name = "MicroMipsMemSP";
88  let RenderMethod = "addMemOperands";
89  let ParserMethod = "parseMemOperand";
90  let PredicateMethod = "isMemWithUimmWordAlignedOffsetSP<7>";
91}
92
93def mem_mm_sp_imm5_lsl2 : Operand<i32> {
94  let PrintMethod = "printMemOperand";
95  let MIOperandInfo = (ops GPR32:$base, simm5:$offset);
96  let OperandType = "OPERAND_MEMORY";
97  let ParserMatchClass = MicroMipsMemSPAsmOperand;
98  let EncoderMethod = "getMemEncodingMMSPImm5Lsl2";
99}
100
101def mem_mm_gp_imm7_lsl2 : Operand<i32> {
102  let PrintMethod = "printMemOperand";
103  let MIOperandInfo = (ops GPRMM16:$base, simm7:$offset);
104  let OperandType = "OPERAND_MEMORY";
105  let EncoderMethod = "getMemEncodingMMGPImm7Lsl2";
106}
107
108def mem_mm_12 : Operand<i32> {
109  let PrintMethod = "printMemOperand";
110  let MIOperandInfo = (ops GPR32, simm12);
111  let EncoderMethod = "getMemEncodingMMImm12";
112  let ParserMatchClass = MipsMemAsmOperand;
113  let OperandType = "OPERAND_MEMORY";
114}
115
116def MipsMemUimm4AsmOperand : AsmOperandClass {
117  let Name = "MemOffsetUimm4";
118  let SuperClasses = [MipsMemAsmOperand];
119  let RenderMethod = "addMemOperands";
120  let ParserMethod = "parseMemOperand";
121  let PredicateMethod = "isMemWithUimmOffsetSP<6>";
122}
123
124def mem_mm_4sp : Operand<i32> {
125  let PrintMethod = "printMemOperand";
126  let MIOperandInfo = (ops GPR32, uimm8);
127  let EncoderMethod = "getMemEncodingMMImm4sp";
128  let ParserMatchClass = MipsMemUimm4AsmOperand;
129  let OperandType = "OPERAND_MEMORY";
130}
131
132def jmptarget_mm : Operand<OtherVT> {
133  let EncoderMethod = "getJumpTargetOpValueMM";
134}
135
136def calltarget_mm : Operand<iPTR> {
137  let EncoderMethod = "getJumpTargetOpValueMM";
138}
139
140def brtarget7_mm : Operand<OtherVT> {
141  let EncoderMethod = "getBranchTarget7OpValueMM";
142  let OperandType   = "OPERAND_PCREL";
143  let DecoderMethod = "DecodeBranchTarget7MM";
144  let ParserMatchClass = MipsJumpTargetAsmOperand;
145}
146
147def brtarget10_mm : Operand<OtherVT> {
148  let EncoderMethod = "getBranchTargetOpValueMMPC10";
149  let OperandType   = "OPERAND_PCREL";
150  let DecoderMethod = "DecodeBranchTarget10MM";
151  let ParserMatchClass = MipsJumpTargetAsmOperand;
152}
153
154def brtarget_mm : Operand<OtherVT> {
155  let EncoderMethod = "getBranchTargetOpValueMM";
156  let OperandType   = "OPERAND_PCREL";
157  let DecoderMethod = "DecodeBranchTargetMM";
158  let ParserMatchClass = MipsJumpTargetAsmOperand;
159}
160
161def simm23_lsl2 : Operand<i32> {
162  let EncoderMethod = "getSimm23Lsl2Encoding";
163  let DecoderMethod = "DecodeSimm23Lsl2";
164}
165
166class CompactBranchMM<string opstr, DAGOperand opnd, PatFrag cond_op,
167                      RegisterOperand RO> :
168  InstSE<(outs), (ins RO:$rs, opnd:$offset),
169         !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI> {
170  let isBranch = 1;
171  let isTerminator = 1;
172  let hasDelaySlot = 0;
173  let Defs = [AT];
174}
175
176let canFoldAsLoad = 1 in
177class LoadLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
178                      Operand MemOpnd> :
179  InstSE<(outs RO:$rt), (ins MemOpnd:$addr, RO:$src),
180         !strconcat(opstr, "\t$rt, $addr"),
181         [(set RO:$rt, (OpNode addrimm12:$addr, RO:$src))],
182         NoItinerary, FrmI> {
183  let DecoderMethod = "DecodeMemMMImm12";
184  string Constraints = "$src = $rt";
185}
186
187class StoreLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
188                       Operand MemOpnd>:
189  InstSE<(outs), (ins RO:$rt, MemOpnd:$addr),
190         !strconcat(opstr, "\t$rt, $addr"),
191         [(OpNode RO:$rt, addrimm12:$addr)], NoItinerary, FrmI> {
192  let DecoderMethod = "DecodeMemMMImm12";
193}
194
195/// A register pair used by movep instruction.
196def MovePRegPairAsmOperand : AsmOperandClass {
197  let Name = "MovePRegPair";
198  let ParserMethod = "parseMovePRegPair";
199  let PredicateMethod = "isMovePRegPair";
200}
201
202def movep_regpair : Operand<i32> {
203  let EncoderMethod = "getMovePRegPairOpValue";
204  let ParserMatchClass = MovePRegPairAsmOperand;
205  let PrintMethod = "printRegisterList";
206  let DecoderMethod = "DecodeMovePRegPair";
207  let MIOperandInfo = (ops GPR32Opnd, GPR32Opnd);
208}
209
210class MovePMM16<string opstr, RegisterOperand RO> :
211MicroMipsInst16<(outs movep_regpair:$dst_regs), (ins RO:$rs, RO:$rt),
212                 !strconcat(opstr, "\t$dst_regs, $rs, $rt"), [],
213                 NoItinerary, FrmR> {
214  let isReMaterializable = 1;
215}
216
217/// A register pair used by load/store pair instructions.
218def RegPairAsmOperand : AsmOperandClass {
219  let Name = "RegPair";
220  let ParserMethod = "parseRegisterPair";
221}
222
223def regpair : Operand<i32> {
224  let EncoderMethod = "getRegisterPairOpValue";
225  let ParserMatchClass = RegPairAsmOperand;
226  let PrintMethod = "printRegisterPair";
227  let DecoderMethod = "DecodeRegPairOperand";
228  let MIOperandInfo = (ops GPR32Opnd, GPR32Opnd);
229}
230
231class StorePairMM<string opstr, InstrItinClass Itin = NoItinerary,
232                  ComplexPattern Addr = addr> :
233  InstSE<(outs), (ins regpair:$rt, mem_mm_12:$addr),
234         !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI, opstr> {
235  let DecoderMethod = "DecodeMemMMImm12";
236  let mayStore = 1;
237}
238
239class LoadPairMM<string opstr, InstrItinClass Itin = NoItinerary,
240                 ComplexPattern Addr = addr> :
241  InstSE<(outs regpair:$rt), (ins mem_mm_12:$addr),
242          !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI, opstr> {
243  let DecoderMethod = "DecodeMemMMImm12";
244  let mayLoad = 1;
245}
246
247class LLBaseMM<string opstr, RegisterOperand RO> :
248  InstSE<(outs RO:$rt), (ins mem_mm_12:$addr),
249         !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
250  let DecoderMethod = "DecodeMemMMImm12";
251  let mayLoad = 1;
252}
253
254class SCBaseMM<string opstr, RegisterOperand RO> :
255  InstSE<(outs RO:$dst), (ins RO:$rt, mem_mm_12:$addr),
256         !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
257  let DecoderMethod = "DecodeMemMMImm12";
258  let mayStore = 1;
259  let Constraints = "$rt = $dst";
260}
261
262class LoadMM<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
263             InstrItinClass Itin = NoItinerary> :
264  InstSE<(outs RO:$rt), (ins mem_mm_12:$addr),
265         !strconcat(opstr, "\t$rt, $addr"),
266         [(set RO:$rt, (OpNode addrimm12:$addr))], Itin, FrmI> {
267  let DecoderMethod = "DecodeMemMMImm12";
268  let canFoldAsLoad = 1;
269  let mayLoad = 1;
270}
271
272class ArithRMM16<string opstr, RegisterOperand RO, bit isComm = 0,
273                 InstrItinClass Itin = NoItinerary,
274                 SDPatternOperator OpNode = null_frag> :
275  MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, RO:$rt),
276                  !strconcat(opstr, "\t$rd, $rs, $rt"),
277                  [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR> {
278  let isCommutable = isComm;
279}
280
281class AndImmMM16<string opstr, RegisterOperand RO,
282                 InstrItinClass Itin = NoItinerary> :
283  MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, uimm4_andi:$imm),
284                  !strconcat(opstr, "\t$rd, $rs, $imm"), [], Itin, FrmI>;
285
286class LogicRMM16<string opstr, RegisterOperand RO,
287                 InstrItinClass Itin = NoItinerary,
288                 SDPatternOperator OpNode = null_frag> :
289  MicroMipsInst16<(outs RO:$dst), (ins RO:$rs, RO:$rt),
290         !strconcat(opstr, "\t$rt, $rs"),
291         [(set RO:$dst, (OpNode RO:$rs, RO:$rt))], Itin, FrmR> {
292  let isCommutable = 1;
293  let Constraints = "$rt = $dst";
294}
295
296class NotMM16<string opstr, RegisterOperand RO> :
297  MicroMipsInst16<(outs RO:$rt), (ins RO:$rs),
298         !strconcat(opstr, "\t$rt, $rs"),
299         [(set RO:$rt, (not RO:$rs))], NoItinerary, FrmR>;
300
301class ShiftIMM16<string opstr, Operand ImmOpnd, RegisterOperand RO,
302                 InstrItinClass Itin = NoItinerary> :
303  MicroMipsInst16<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
304                  !strconcat(opstr, "\t$rd, $rt, $shamt"), [], Itin, FrmR>;
305
306class LoadMM16<string opstr, DAGOperand RO, SDPatternOperator OpNode,
307               InstrItinClass Itin, Operand MemOpnd> :
308  MicroMipsInst16<(outs RO:$rt), (ins MemOpnd:$addr),
309                  !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
310  let DecoderMethod = "DecodeMemMMImm4";
311  let canFoldAsLoad = 1;
312  let mayLoad = 1;
313}
314
315class StoreMM16<string opstr, DAGOperand RTOpnd, DAGOperand RO,
316                SDPatternOperator OpNode, InstrItinClass Itin,
317                Operand MemOpnd> :
318  MicroMipsInst16<(outs), (ins RTOpnd:$rt, MemOpnd:$addr),
319                  !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
320  let DecoderMethod = "DecodeMemMMImm4";
321  let mayStore = 1;
322}
323
324class LoadSPMM16<string opstr, DAGOperand RO, InstrItinClass Itin,
325                 Operand MemOpnd> :
326  MicroMipsInst16<(outs RO:$rt), (ins MemOpnd:$offset),
327                  !strconcat(opstr, "\t$rt, $offset"), [], Itin, FrmI> {
328  let DecoderMethod = "DecodeMemMMSPImm5Lsl2";
329  let canFoldAsLoad = 1;
330  let mayLoad = 1;
331}
332
333class StoreSPMM16<string opstr, DAGOperand RO, InstrItinClass Itin,
334                  Operand MemOpnd> :
335  MicroMipsInst16<(outs), (ins RO:$rt, MemOpnd:$offset),
336                  !strconcat(opstr, "\t$rt, $offset"), [], Itin, FrmI> {
337  let DecoderMethod = "DecodeMemMMSPImm5Lsl2";
338  let mayStore = 1;
339}
340
341class LoadGPMM16<string opstr, DAGOperand RO, InstrItinClass Itin,
342                 Operand MemOpnd> :
343  MicroMipsInst16<(outs RO:$rt), (ins MemOpnd:$offset),
344                  !strconcat(opstr, "\t$rt, $offset"), [], Itin, FrmI> {
345  let DecoderMethod = "DecodeMemMMGPImm7Lsl2";
346  let canFoldAsLoad = 1;
347  let mayLoad = 1;
348}
349
350class AddImmUR2<string opstr, RegisterOperand RO> :
351  MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, simm3_lsa2:$imm),
352                  !strconcat(opstr, "\t$rd, $rs, $imm"),
353                  [], NoItinerary, FrmR> {
354  let isCommutable = 1;
355}
356
357class AddImmUS5<string opstr, RegisterOperand RO> :
358  MicroMipsInst16<(outs RO:$dst), (ins RO:$rd, simm4:$imm),
359                  !strconcat(opstr, "\t$rd, $imm"), [], NoItinerary, FrmR> {
360  let Constraints = "$rd = $dst";
361}
362
363class AddImmUR1SP<string opstr, RegisterOperand RO> :
364  MicroMipsInst16<(outs RO:$rd), (ins uimm6_lsl2:$imm),
365                  !strconcat(opstr, "\t$rd, $imm"), [], NoItinerary, FrmR>;
366
367class AddImmUSP<string opstr> :
368  MicroMipsInst16<(outs), (ins simm9_addiusp:$imm),
369                  !strconcat(opstr, "\t$imm"), [], NoItinerary, FrmI>;
370
371class MoveFromHILOMM<string opstr, RegisterOperand RO, Register UseReg> :
372      MicroMipsInst16<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"),
373  [], II_MFHI_MFLO, FrmR> {
374  let Uses = [UseReg];
375  let hasSideEffects = 0;
376}
377
378class MoveMM16<string opstr, RegisterOperand RO, bit isComm = 0,
379               InstrItinClass Itin = NoItinerary> :
380  MicroMipsInst16<(outs RO:$rd), (ins RO:$rs),
381                  !strconcat(opstr, "\t$rd, $rs"), [], Itin, FrmR> {
382  let isCommutable = isComm;
383  let isReMaterializable = 1;
384}
385
386class LoadImmMM16<string opstr, Operand Od, RegisterOperand RO> :
387  MicroMipsInst16<(outs RO:$rd), (ins Od:$imm),
388                  !strconcat(opstr, "\t$rd, $imm"), [], NoItinerary, FrmI> {
389  let isReMaterializable = 1;
390}
391
392// 16-bit Jump and Link (Call)
393class JumpLinkRegMM16<string opstr, RegisterOperand RO> :
394  MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
395           [(MipsJmpLink RO:$rs)], IIBranch, FrmR> {
396  let isCall = 1;
397  let hasDelaySlot = 1;
398  let Defs = [RA];
399}
400
401// 16-bit Jump Reg
402class JumpRegMM16<string opstr, RegisterOperand RO> :
403  MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
404           [], IIBranch, FrmR> {
405  let hasDelaySlot = 1;
406  let isBranch = 1;
407  let isIndirectBranch = 1;
408}
409
410// Base class for JRADDIUSP instruction.
411class JumpRAddiuStackMM16 :
412  MicroMipsInst16<(outs), (ins uimm5_lsl2:$imm), "jraddiusp\t$imm",
413                  [], IIBranch, FrmR> {
414  let isTerminator = 1;
415  let isBarrier = 1;
416  let isBranch = 1;
417  let isIndirectBranch = 1;
418}
419
420// 16-bit Jump and Link (Call) - Short Delay Slot
421class JumpLinkRegSMM16<string opstr, RegisterOperand RO> :
422  MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
423           [], IIBranch, FrmR> {
424  let isCall = 1;
425  let hasDelaySlot = 1;
426  let Defs = [RA];
427}
428
429// 16-bit Jump Register Compact - No delay slot
430class JumpRegCMM16<string opstr, RegisterOperand RO> :
431  MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
432                  [], IIBranch, FrmR> {
433  let isTerminator = 1;
434  let isBarrier = 1;
435  let isBranch = 1;
436  let isIndirectBranch = 1;
437}
438
439// Break16 and Sdbbp16
440class BrkSdbbp16MM<string opstr> :
441  MicroMipsInst16<(outs), (ins uimm4:$code_),
442                  !strconcat(opstr, "\t$code_"),
443                  [], NoItinerary, FrmOther>;
444
445class CBranchZeroMM<string opstr, DAGOperand opnd, RegisterOperand RO> :
446  MicroMipsInst16<(outs), (ins RO:$rs, opnd:$offset),
447                  !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI> {
448  let isBranch = 1;
449  let isTerminator = 1;
450  let hasDelaySlot = 1;
451  let Defs = [AT];
452}
453
454// MicroMIPS Jump and Link (Call) - Short Delay Slot
455let isCall = 1, hasDelaySlot = 1, Defs = [RA] in {
456  class JumpLinkMM<string opstr, DAGOperand opnd> :
457    InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
458           [], IIBranch, FrmJ, opstr> {
459    let DecoderMethod = "DecodeJumpTargetMM";
460  }
461
462  class JumpLinkRegMM<string opstr, RegisterOperand RO>:
463    InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
464            [], IIBranch, FrmR>;
465
466  class BranchCompareToZeroLinkMM<string opstr, DAGOperand opnd,
467                                  RegisterOperand RO> :
468    InstSE<(outs), (ins RO:$rs, opnd:$offset),
469           !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI, opstr>;
470}
471
472class LoadWordIndexedScaledMM<string opstr, RegisterOperand RO,
473                              InstrItinClass Itin = NoItinerary,
474                              SDPatternOperator OpNode = null_frag> :
475  InstSE<(outs RO:$rd), (ins PtrRC:$base, PtrRC:$index),
476         !strconcat(opstr, "\t$rd, ${index}(${base})"), [], Itin, FrmFI>;
477
478class AddImmUPC<string opstr, RegisterOperand RO> :
479  InstSE<(outs RO:$rs), (ins simm23_lsl2:$imm),
480         !strconcat(opstr, "\t$rs, $imm"), [], NoItinerary, FrmR>;
481
482/// A list of registers used by load/store multiple instructions.
483def RegListAsmOperand : AsmOperandClass {
484  let Name = "RegList";
485  let ParserMethod = "parseRegisterList";
486}
487
488def reglist : Operand<i32> {
489  let EncoderMethod = "getRegisterListOpValue";
490  let ParserMatchClass = RegListAsmOperand;
491  let PrintMethod = "printRegisterList";
492  let DecoderMethod = "DecodeRegListOperand";
493}
494
495def RegList16AsmOperand : AsmOperandClass {
496  let Name = "RegList16";
497  let ParserMethod = "parseRegisterList";
498  let PredicateMethod = "isRegList16";
499  let RenderMethod = "addRegListOperands";
500}
501
502def reglist16 : Operand<i32> {
503  let EncoderMethod = "getRegisterListOpValue16";
504  let DecoderMethod = "DecodeRegListOperand16";
505  let PrintMethod = "printRegisterList";
506  let ParserMatchClass = RegList16AsmOperand;
507}
508
509class StoreMultMM<string opstr,
510            InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
511  InstSE<(outs), (ins reglist:$rt, mem_mm_12:$addr),
512         !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI, opstr> {
513  let DecoderMethod = "DecodeMemMMImm12";
514  let mayStore = 1;
515}
516
517class LoadMultMM<string opstr,
518            InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
519  InstSE<(outs reglist:$rt), (ins mem_mm_12:$addr),
520          !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI, opstr> {
521  let DecoderMethod = "DecodeMemMMImm12";
522  let mayLoad = 1;
523}
524
525class StoreMultMM16<string opstr,
526                    InstrItinClass Itin = NoItinerary,
527                    ComplexPattern Addr = addr> :
528  MicroMipsInst16<(outs), (ins reglist16:$rt, mem_mm_4sp:$addr),
529                  !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
530  let DecoderMethod = "DecodeMemMMReglistImm4Lsl2";
531  let mayStore = 1;
532}
533
534class LoadMultMM16<string opstr,
535                   InstrItinClass Itin = NoItinerary,
536                   ComplexPattern Addr = addr> :
537  MicroMipsInst16<(outs reglist16:$rt), (ins mem_mm_4sp:$addr),
538                  !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
539  let DecoderMethod = "DecodeMemMMReglistImm4Lsl2";
540  let mayLoad = 1;
541}
542
543class UncondBranchMM16<string opstr> :
544  MicroMipsInst16<(outs), (ins brtarget10_mm:$offset),
545                  !strconcat(opstr, "\t$offset"),
546                  [], IIBranch, FrmI> {
547  let isBranch = 1;
548  let isTerminator = 1;
549  let isBarrier = 1;
550  let hasDelaySlot = 1;
551  let Predicates = [RelocPIC, InMicroMips];
552  let Defs = [AT];
553}
554
555def ADDU16_MM : ArithRMM16<"addu16", GPRMM16Opnd, 1, II_ADDU, add>,
556                ARITH_FM_MM16<0>;
557def SUBU16_MM : ArithRMM16<"subu16", GPRMM16Opnd, 0, II_SUBU, sub>,
558                ARITH_FM_MM16<1>;
559def ANDI16_MM : AndImmMM16<"andi16", GPRMM16Opnd, II_AND>, ANDI_FM_MM16<0x0b>;
560def AND16_MM : LogicRMM16<"and16", GPRMM16Opnd, II_AND, and>,
561               LOGIC_FM_MM16<0x2>;
562def OR16_MM  : LogicRMM16<"or16", GPRMM16Opnd, II_OR, or>,
563               LOGIC_FM_MM16<0x3>;
564def XOR16_MM : LogicRMM16<"xor16", GPRMM16Opnd, II_XOR, xor>,
565               LOGIC_FM_MM16<0x1>;
566def NOT16_MM : NotMM16<"not16", GPRMM16Opnd>, LOGIC_FM_MM16<0x0>;
567def SLL16_MM : ShiftIMM16<"sll16", uimm3_shift, GPRMM16Opnd, II_SLL>,
568               SHIFT_FM_MM16<0>;
569def SRL16_MM : ShiftIMM16<"srl16", uimm3_shift, GPRMM16Opnd, II_SRL>,
570               SHIFT_FM_MM16<1>;
571def LBU16_MM : LoadMM16<"lbu16", GPRMM16Opnd, zextloadi8, II_LBU,
572                        mem_mm_4>, LOAD_STORE_FM_MM16<0x02>;
573def LHU16_MM : LoadMM16<"lhu16", GPRMM16Opnd, zextloadi16, II_LHU,
574                        mem_mm_4_lsl1>, LOAD_STORE_FM_MM16<0x0a>;
575def LW16_MM : LoadMM16<"lw16", GPRMM16Opnd, load, II_LW, mem_mm_4_lsl2>,
576                      LOAD_STORE_FM_MM16<0x1a>;
577def SB16_MM : StoreMM16<"sb16", GPRMM16OpndZero, GPRMM16Opnd, truncstorei8,
578                        II_SB, mem_mm_4>, LOAD_STORE_FM_MM16<0x22>;
579def SH16_MM : StoreMM16<"sh16", GPRMM16OpndZero, GPRMM16Opnd, truncstorei16,
580                        II_SH, mem_mm_4_lsl1>,
581                        LOAD_STORE_FM_MM16<0x2a>;
582def SW16_MM : StoreMM16<"sw16", GPRMM16OpndZero, GPRMM16Opnd, store, II_SW,
583                        mem_mm_4_lsl2>, LOAD_STORE_FM_MM16<0x3a>;
584def LWGP_MM : LoadGPMM16<"lw", GPRMM16Opnd, II_LW, mem_mm_gp_imm7_lsl2>,
585                         LOAD_GP_FM_MM16<0x19>;
586def LWSP_MM : LoadSPMM16<"lw", GPR32Opnd, II_LW, mem_mm_sp_imm5_lsl2>,
587              LOAD_STORE_SP_FM_MM16<0x12>;
588def SWSP_MM : StoreSPMM16<"sw", GPR32Opnd, II_SW, mem_mm_sp_imm5_lsl2>,
589              LOAD_STORE_SP_FM_MM16<0x32>;
590def ADDIUR1SP_MM : AddImmUR1SP<"addiur1sp", GPRMM16Opnd>, ADDIUR1SP_FM_MM16;
591def ADDIUR2_MM : AddImmUR2<"addiur2", GPRMM16Opnd>, ADDIUR2_FM_MM16;
592def ADDIUS5_MM : AddImmUS5<"addius5", GPR32Opnd>, ADDIUS5_FM_MM16;
593def ADDIUSP_MM : AddImmUSP<"addiusp">, ADDIUSP_FM_MM16;
594def MFHI16_MM : MoveFromHILOMM<"mfhi", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x10>;
595def MFLO16_MM : MoveFromHILOMM<"mflo", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x12>;
596def MOVE16_MM : MoveMM16<"move", GPR32Opnd>, MOVE_FM_MM16<0x03>;
597def MOVEP_MM : MovePMM16<"movep", GPRMM16OpndMoveP>, MOVEP_FM_MM16;
598def LI16_MM : LoadImmMM16<"li16", li_simm7, GPRMM16Opnd>, LI_FM_MM16,
599              IsAsCheapAsAMove;
600def JALR16_MM : JumpLinkRegMM16<"jalr", GPR32Opnd>, JALR_FM_MM16<0x0e>;
601def JALRS16_MM : JumpLinkRegSMM16<"jalrs16", GPR32Opnd>, JALR_FM_MM16<0x0f>;
602def JRC16_MM : JumpRegCMM16<"jrc", GPR32Opnd>, JALR_FM_MM16<0x0d>;
603def JRADDIUSP : JumpRAddiuStackMM16, JRADDIUSP_FM_MM16<0x18>;
604def JR16_MM : JumpRegMM16<"jr16", GPR32Opnd>, JALR_FM_MM16<0x0c>;
605def BEQZ16_MM : CBranchZeroMM<"beqz16", brtarget7_mm, GPRMM16Opnd>,
606                BEQNEZ_FM_MM16<0x23>;
607def BNEZ16_MM : CBranchZeroMM<"bnez16", brtarget7_mm, GPRMM16Opnd>,
608                BEQNEZ_FM_MM16<0x2b>;
609def B16_MM : UncondBranchMM16<"b16">, B16_FM;
610def BREAK16_MM : BrkSdbbp16MM<"break16">, BRKSDBBP16_FM_MM<0x28>;
611def SDBBP16_MM : BrkSdbbp16MM<"sdbbp16">, BRKSDBBP16_FM_MM<0x2C>;
612
613class WaitMM<string opstr> :
614  InstSE<(outs), (ins uimm10:$code_), !strconcat(opstr, "\t$code_"), [],
615         NoItinerary, FrmOther, opstr>;
616
617let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
618  /// Compact Branch Instructions
619  def BEQZC_MM : CompactBranchMM<"beqzc", brtarget_mm, seteq, GPR32Opnd>,
620                 COMPACT_BRANCH_FM_MM<0x7>;
621  def BNEZC_MM : CompactBranchMM<"bnezc", brtarget_mm, setne, GPR32Opnd>,
622                 COMPACT_BRANCH_FM_MM<0x5>;
623
624  /// Arithmetic Instructions (ALU Immediate)
625  def ADDiu_MM : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd>,
626                 ADDI_FM_MM<0xc>;
627  def ADDi_MM  : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>,
628                 ADDI_FM_MM<0x4>;
629  def SLTi_MM  : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
630                 SLTI_FM_MM<0x24>;
631  def SLTiu_MM : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
632                 SLTI_FM_MM<0x2c>;
633  def ANDi_MM  : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd>,
634                 ADDI_FM_MM<0x34>;
635  def ORi_MM   : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd>,
636                 ADDI_FM_MM<0x14>;
637  def XORi_MM  : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd>,
638                 ADDI_FM_MM<0x1c>;
639  def LUi_MM   : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM_MM;
640
641  def LEA_ADDiu_MM : MMRel, EffectiveAddress<"addiu", GPR32Opnd>,
642                     LW_FM_MM<0xc>;
643
644  /// Arithmetic Instructions (3-Operand, R-Type)
645  def ADDu_MM  : MMRel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>,
646                 ADD_FM_MM<0, 0x150>;
647  def SUBu_MM  : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>,
648                 ADD_FM_MM<0, 0x1d0>;
649  def MUL_MM   : MMRel, ArithLogicR<"mul", GPR32Opnd>, ADD_FM_MM<0, 0x210>;
650  def ADD_MM   : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM_MM<0, 0x110>;
651  def SUB_MM   : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM_MM<0, 0x190>;
652  def SLT_MM   : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM_MM<0, 0x350>;
653  def SLTu_MM  : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>,
654                 ADD_FM_MM<0, 0x390>;
655  def AND_MM   : MMRel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
656                 ADD_FM_MM<0, 0x250>;
657  def OR_MM    : MMRel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,
658                 ADD_FM_MM<0, 0x290>;
659  def XOR_MM   : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
660                 ADD_FM_MM<0, 0x310>;
661  def NOR_MM   : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM_MM<0, 0x2d0>;
662  def MULT_MM  : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>,
663                 MULT_FM_MM<0x22c>;
664  def MULTu_MM : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>,
665                 MULT_FM_MM<0x26c>;
666  def SDIV_MM  : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>,
667                 MULT_FM_MM<0x2ac>;
668  def UDIV_MM  : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>,
669                 MULT_FM_MM<0x2ec>;
670
671  /// Arithmetic Instructions with PC and Immediate
672  def ADDIUPC_MM : AddImmUPC<"addiupc", GPRMM16Opnd>, ADDIUPC_FM_MM;
673
674  /// Shift Instructions
675  def SLL_MM   : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL>,
676                 SRA_FM_MM<0, 0>;
677  def SRL_MM   : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL>,
678                 SRA_FM_MM<0x40, 0>;
679  def SRA_MM   : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA>,
680                 SRA_FM_MM<0x80, 0>;
681  def SLLV_MM  : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV>,
682                 SRLV_FM_MM<0x10, 0>;
683  def SRLV_MM  : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV>,
684                 SRLV_FM_MM<0x50, 0>;
685  def SRAV_MM  : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV>,
686                 SRLV_FM_MM<0x90, 0>;
687  def ROTR_MM  : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR>,
688                 SRA_FM_MM<0xc0, 0>;
689  def ROTRV_MM : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV>,
690                 SRLV_FM_MM<0xd0, 0>;
691
692  /// Load and Store Instructions - aligned
693  let DecoderMethod = "DecodeMemMMImm16" in {
694    def LB_MM  : Load<"lb", GPR32Opnd>, MMRel, LW_FM_MM<0x7>;
695    def LBu_MM : Load<"lbu", GPR32Opnd>, MMRel, LW_FM_MM<0x5>;
696    def LH_MM  : Load<"lh", GPR32Opnd>, MMRel, LW_FM_MM<0xf>;
697    def LHu_MM : Load<"lhu", GPR32Opnd>, MMRel, LW_FM_MM<0xd>;
698    def LW_MM  : Load<"lw", GPR32Opnd>, MMRel, LW_FM_MM<0x3f>;
699    def SB_MM  : Store<"sb", GPR32Opnd>, MMRel, LW_FM_MM<0x6>;
700    def SH_MM  : Store<"sh", GPR32Opnd>, MMRel, LW_FM_MM<0xe>;
701    def SW_MM  : Store<"sw", GPR32Opnd>, MMRel, LW_FM_MM<0x3e>;
702  }
703
704  def LWXS_MM : LoadWordIndexedScaledMM<"lwxs", GPR32Opnd>, LWXS_FM_MM<0x118>;
705
706  def LWU_MM : LoadMM<"lwu", GPR32Opnd, zextloadi32, II_LWU>, LL_FM_MM<0xe>;
707
708  /// Load and Store Instructions - unaligned
709  def LWL_MM : LoadLeftRightMM<"lwl", MipsLWL, GPR32Opnd, mem_mm_12>,
710               LWL_FM_MM<0x0>;
711  def LWR_MM : LoadLeftRightMM<"lwr", MipsLWR, GPR32Opnd, mem_mm_12>,
712               LWL_FM_MM<0x1>;
713  def SWL_MM : StoreLeftRightMM<"swl", MipsSWL, GPR32Opnd, mem_mm_12>,
714               LWL_FM_MM<0x8>;
715  def SWR_MM : StoreLeftRightMM<"swr", MipsSWR, GPR32Opnd, mem_mm_12>,
716               LWL_FM_MM<0x9>;
717
718  /// Load and Store Instructions - multiple
719  def SWM32_MM  : StoreMultMM<"swm32">, LWM_FM_MM<0xd>;
720  def LWM32_MM  : LoadMultMM<"lwm32">, LWM_FM_MM<0x5>;
721  def SWM16_MM : StoreMultMM16<"swm16">, LWM_FM_MM16<0x5>;
722  def LWM16_MM : LoadMultMM16<"lwm16">, LWM_FM_MM16<0x4>;
723
724  /// Load and Store Pair Instructions
725  def SWP_MM  : StorePairMM<"swp">, LWM_FM_MM<0x9>;
726  def LWP_MM  : LoadPairMM<"lwp">, LWM_FM_MM<0x1>;
727
728  /// Load and Store multiple pseudo Instructions
729  class LoadWordMultMM<string instr_asm > :
730    MipsAsmPseudoInst<(outs reglist:$rt), (ins mem_mm_12:$addr),
731                      !strconcat(instr_asm, "\t$rt, $addr")> ;
732
733  class StoreWordMultMM<string instr_asm > :
734    MipsAsmPseudoInst<(outs), (ins reglist:$rt, mem_mm_12:$addr),
735                      !strconcat(instr_asm, "\t$rt, $addr")> ;
736
737
738  def SWM_MM  : StoreWordMultMM<"swm">;
739  def LWM_MM  : LoadWordMultMM<"lwm">;
740
741  /// Move Conditional
742  def MOVZ_I_MM : MMRel, CMov_I_I_FT<"movz", GPR32Opnd, GPR32Opnd,
743                  NoItinerary>, ADD_FM_MM<0, 0x58>;
744  def MOVN_I_MM : MMRel, CMov_I_I_FT<"movn", GPR32Opnd, GPR32Opnd,
745                  NoItinerary>, ADD_FM_MM<0, 0x18>;
746  def MOVT_I_MM : MMRel, CMov_F_I_FT<"movt", GPR32Opnd, II_MOVT>,
747                  CMov_F_I_FM_MM<0x25>;
748  def MOVF_I_MM : MMRel, CMov_F_I_FT<"movf", GPR32Opnd, II_MOVF>,
749                  CMov_F_I_FM_MM<0x5>;
750
751  /// Move to/from HI/LO
752  def MTHI_MM : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>,
753                MTLO_FM_MM<0x0b5>;
754  def MTLO_MM : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>,
755                MTLO_FM_MM<0x0f5>;
756  def MFHI_MM : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>,
757                MFLO_FM_MM<0x035>;
758  def MFLO_MM : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>,
759                MFLO_FM_MM<0x075>;
760
761  /// Multiply Add/Sub Instructions
762  def MADD_MM  : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM_MM<0x32c>;
763  def MADDU_MM : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM_MM<0x36c>;
764  def MSUB_MM  : MMRel, MArithR<"msub", II_MSUB>, MULT_FM_MM<0x3ac>;
765  def MSUBU_MM : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM_MM<0x3ec>;
766
767  /// Count Leading
768  def CLZ_MM : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM_MM<0x16c>,
769               ISA_MIPS32;
770  def CLO_MM : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM_MM<0x12c>,
771               ISA_MIPS32;
772
773  /// Sign Ext In Register Instructions.
774  def SEB_MM : MMRel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>,
775               SEB_FM_MM<0x0ac>, ISA_MIPS32R2;
776  def SEH_MM : MMRel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>,
777               SEB_FM_MM<0x0ec>, ISA_MIPS32R2;
778
779  /// Word Swap Bytes Within Halfwords
780  def WSBH_MM : MMRel, SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM_MM<0x1ec>,
781                ISA_MIPS32R2;
782
783  def EXT_MM : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>,
784               EXT_FM_MM<0x2c>;
785  def INS_MM : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>,
786               EXT_FM_MM<0x0c>;
787
788  /// Jump Instructions
789  let DecoderMethod = "DecodeJumpTargetMM" in {
790    def J_MM        : MMRel, JumpFJ<jmptarget_mm, "j", br, bb, "j">,
791                      J_FM_MM<0x35>;
792    def JAL_MM      : MMRel, JumpLink<"jal", calltarget_mm>, J_FM_MM<0x3d>;
793    def JALX_MM     : MMRel, JumpLink<"jalx", calltarget>, J_FM_MM<0x3c>;
794  }
795  def JR_MM   : MMRel, IndirectBranch<"jr", GPR32Opnd>, JR_FM_MM<0x3c>;
796  def JALR_MM : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM_MM<0x03c>;
797
798  /// Jump Instructions - Short Delay Slot
799  def JALS_MM   : JumpLinkMM<"jals", calltarget_mm>, J_FM_MM<0x1d>;
800  def JALRS_MM  : JumpLinkRegMM<"jalrs", GPR32Opnd>, JALR_FM_MM<0x13c>;
801
802  /// Branch Instructions
803  def BEQ_MM  : MMRel, CBranch<"beq", brtarget_mm, seteq, GPR32Opnd>,
804                BEQ_FM_MM<0x25>;
805  def BNE_MM  : MMRel, CBranch<"bne", brtarget_mm, setne, GPR32Opnd>,
806                BEQ_FM_MM<0x2d>;
807  def BGEZ_MM : MMRel, CBranchZero<"bgez", brtarget_mm, setge, GPR32Opnd>,
808                BGEZ_FM_MM<0x2>;
809  def BGTZ_MM : MMRel, CBranchZero<"bgtz", brtarget_mm, setgt, GPR32Opnd>,
810                BGEZ_FM_MM<0x6>;
811  def BLEZ_MM : MMRel, CBranchZero<"blez", brtarget_mm, setle, GPR32Opnd>,
812                BGEZ_FM_MM<0x4>;
813  def BLTZ_MM : MMRel, CBranchZero<"bltz", brtarget_mm, setlt, GPR32Opnd>,
814                BGEZ_FM_MM<0x0>;
815  def BGEZAL_MM : MMRel, BGEZAL_FT<"bgezal", brtarget_mm, GPR32Opnd>,
816                  BGEZAL_FM_MM<0x03>;
817  def BLTZAL_MM : MMRel, BGEZAL_FT<"bltzal", brtarget_mm, GPR32Opnd>,
818                  BGEZAL_FM_MM<0x01>;
819
820  /// Branch Instructions - Short Delay Slot
821  def BGEZALS_MM : BranchCompareToZeroLinkMM<"bgezals", brtarget_mm,
822                                             GPR32Opnd>, BGEZAL_FM_MM<0x13>;
823  def BLTZALS_MM : BranchCompareToZeroLinkMM<"bltzals", brtarget_mm,
824                                             GPR32Opnd>, BGEZAL_FM_MM<0x11>;
825
826  /// Control Instructions
827  def SYNC_MM    : MMRel, SYNC_FT<"sync">, SYNC_FM_MM;
828  def BREAK_MM   : MMRel, BRK_FT<"break">, BRK_FM_MM;
829  def SYSCALL_MM : MMRel, SYS_FT<"syscall">, SYS_FM_MM;
830  def WAIT_MM    : WaitMM<"wait">, WAIT_FM_MM;
831  def ERET_MM    : MMRel, ER_FT<"eret">, ER_FM_MM<0x3cd>;
832  def DERET_MM   : MMRel, ER_FT<"deret">, ER_FM_MM<0x38d>;
833  def EI_MM      : MMRel, DEI_FT<"ei", GPR32Opnd>, EI_FM_MM<0x15d>,
834                   ISA_MIPS32R2;
835  def DI_MM      : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM_MM<0x11d>,
836                   ISA_MIPS32R2;
837
838  /// Trap Instructions
839  def TEQ_MM  : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM_MM<0x0>;
840  def TGE_MM  : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM_MM<0x08>;
841  def TGEU_MM : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM_MM<0x10>;
842  def TLT_MM  : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM_MM<0x20>;
843  def TLTU_MM : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM_MM<0x28>;
844  def TNE_MM  : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM_MM<0x30>;
845
846  def TEQI_MM  : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM_MM<0x0e>;
847  def TGEI_MM  : MMRel, TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM_MM<0x09>;
848  def TGEIU_MM : MMRel, TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM_MM<0x0b>;
849  def TLTI_MM  : MMRel, TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM_MM<0x08>;
850  def TLTIU_MM : MMRel, TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM_MM<0x0a>;
851  def TNEI_MM  : MMRel, TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM_MM<0x0c>;
852
853  /// Load-linked, Store-conditional
854  def LL_MM : LLBaseMM<"ll", GPR32Opnd>, LL_FM_MM<0x3>;
855  def SC_MM : SCBaseMM<"sc", GPR32Opnd>, LL_FM_MM<0xb>;
856
857  let DecoderMethod = "DecodeCacheOpMM" in {
858  def CACHE_MM : MMRel, CacheOp<"cache", mem_mm_12>,
859                 CACHE_PREF_FM_MM<0x08, 0x6>;
860  def PREF_MM  : MMRel, CacheOp<"pref", mem_mm_12>,
861                 CACHE_PREF_FM_MM<0x18, 0x2>;
862  }
863  def SSNOP_MM : MMRel, Barrier<"ssnop">, BARRIER_FM_MM<0x1>;
864  def EHB_MM   : MMRel, Barrier<"ehb">, BARRIER_FM_MM<0x3>;
865  def PAUSE_MM : MMRel, Barrier<"pause">, BARRIER_FM_MM<0x5>;
866
867  def TLBP_MM : MMRel, TLB<"tlbp">, COP0_TLB_FM_MM<0x0d>;
868  def TLBR_MM : MMRel, TLB<"tlbr">, COP0_TLB_FM_MM<0x4d>;
869  def TLBWI_MM : MMRel, TLB<"tlbwi">, COP0_TLB_FM_MM<0x8d>;
870  def TLBWR_MM : MMRel, TLB<"tlbwr">, COP0_TLB_FM_MM<0xcd>;
871
872  def SDBBP_MM : MMRel, SYS_FT<"sdbbp">, SDBBP_FM_MM;
873  def RDHWR_MM : MMRel, ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM_MM;
874}
875
876let Predicates = [InMicroMips] in {
877
878//===----------------------------------------------------------------------===//
879// MicroMips arbitrary patterns that map to one or more instructions
880//===----------------------------------------------------------------------===//
881
882def : MipsPat<(i32 immLi16:$imm),
883              (LI16_MM immLi16:$imm)>;
884def : MipsPat<(i32 immSExt16:$imm),
885              (ADDiu_MM ZERO, immSExt16:$imm)>;
886def : MipsPat<(i32 immZExt16:$imm),
887              (ORi_MM ZERO, immZExt16:$imm)>;
888def : MipsPat<(not GPR32:$in),
889              (NOR_MM GPR32Opnd:$in, ZERO)>;
890
891def : MipsPat<(add GPRMM16:$src, immSExtAddiur2:$imm),
892              (ADDIUR2_MM GPRMM16:$src, immSExtAddiur2:$imm)>;
893def : MipsPat<(add GPR32:$src, immSExtAddius5:$imm),
894              (ADDIUS5_MM GPR32:$src, immSExtAddius5:$imm)>;
895def : MipsPat<(add GPR32:$src, immSExt16:$imm),
896              (ADDiu_MM GPR32:$src, immSExt16:$imm)>;
897
898def : MipsPat<(and GPRMM16:$src, immZExtAndi16:$imm),
899              (ANDI16_MM GPRMM16:$src, immZExtAndi16:$imm)>;
900def : MipsPat<(and GPR32:$src, immZExt16:$imm),
901              (ANDi_MM GPR32:$src, immZExt16:$imm)>;
902
903def : MipsPat<(shl GPRMM16:$src, immZExt2Shift:$imm),
904              (SLL16_MM GPRMM16:$src, immZExt2Shift:$imm)>;
905def : MipsPat<(shl GPR32:$src, immZExt5:$imm),
906              (SLL_MM GPR32:$src, immZExt5:$imm)>;
907
908def : MipsPat<(srl GPRMM16:$src, immZExt2Shift:$imm),
909              (SRL16_MM GPRMM16:$src, immZExt2Shift:$imm)>;
910def : MipsPat<(srl GPR32:$src, immZExt5:$imm),
911              (SRL_MM GPR32:$src, immZExt5:$imm)>;
912
913def : MipsPat<(store GPRMM16:$src, addrimm4lsl2:$addr),
914              (SW16_MM GPRMM16:$src, addrimm4lsl2:$addr)>;
915def : MipsPat<(store GPR32:$src, addr:$addr),
916              (SW_MM GPR32:$src, addr:$addr)>;
917
918def : MipsPat<(load addrimm4lsl2:$addr),
919              (LW16_MM addrimm4lsl2:$addr)>;
920def : MipsPat<(load addr:$addr),
921              (LW_MM addr:$addr)>;
922
923//===----------------------------------------------------------------------===//
924// MicroMips instruction aliases
925//===----------------------------------------------------------------------===//
926
927class UncondBranchMMPseudo<string opstr> :
928  MipsAsmPseudoInst<(outs), (ins brtarget_mm:$offset),
929                    !strconcat(opstr, "\t$offset")>;
930
931  def B_MM_Pseudo : UncondBranchMMPseudo<"b">;
932
933  def : MipsInstAlias<"wait", (WAIT_MM 0x0), 1>;
934  def : MipsInstAlias<"nop", (SLL_MM ZERO, ZERO, 0), 1>;
935  def : MipsInstAlias<"nop", (MOVE16_MM ZERO, ZERO), 1>;
936}
937