1//===-- MipsInstrFormats.td - Mips Instruction Formats -----*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// Describe MIPS instructions format 12// 13// CPU INSTRUCTION FORMATS 14// 15// opcode - operation code. 16// rs - src reg. 17// rt - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr). 18// rd - dst reg, only used on 3 regs instr. 19// shamt - only used on shift instructions, contains the shift amount. 20// funct - combined with opcode field give us an operation code. 21// 22//===----------------------------------------------------------------------===// 23 24// Format specifies the encoding used by the instruction. This is part of the 25// ad-hoc solution used to emit machine instruction encodings by our machine 26// code emitter. 27class Format<bits<4> val> { 28 bits<4> Value = val; 29} 30 31def Pseudo : Format<0>; 32def FrmR : Format<1>; 33def FrmI : Format<2>; 34def FrmJ : Format<3>; 35def FrmFR : Format<4>; 36def FrmFI : Format<5>; 37def FrmOther : Format<6>; // Instruction w/ a custom format 38 39class MMRel; 40 41def Std2MicroMips : InstrMapping { 42 let FilterClass = "MMRel"; 43 // Instructions with the same BaseOpcode and isNVStore values form a row. 44 let RowFields = ["BaseOpcode"]; 45 // Instructions with the same predicate sense form a column. 46 let ColFields = ["Arch"]; 47 // The key column is the unpredicated instructions. 48 let KeyCol = ["se"]; 49 // Value columns are PredSense=true and PredSense=false 50 let ValueCols = [["se"], ["micromips"]]; 51} 52 53class StdArch { 54 string Arch = "se"; 55} 56 57// Generic Mips Format 58class MipsInst<dag outs, dag ins, string asmstr, list<dag> pattern, 59 InstrItinClass itin, Format f>: Instruction 60{ 61 field bits<32> Inst; 62 Format Form = f; 63 64 let Namespace = "Mips"; 65 66 let Size = 4; 67 68 bits<6> Opcode = 0; 69 70 // Top 6 bits are the 'opcode' field 71 let Inst{31-26} = Opcode; 72 73 let OutOperandList = outs; 74 let InOperandList = ins; 75 76 let AsmString = asmstr; 77 let Pattern = pattern; 78 let Itinerary = itin; 79 80 // 81 // Attributes specific to Mips instructions... 82 // 83 bits<4> FormBits = Form.Value; 84 85 // TSFlags layout should be kept in sync with MipsInstrInfo.h. 86 let TSFlags{3-0} = FormBits; 87 88 let DecoderNamespace = "Mips"; 89 90 field bits<32> SoftFail = 0; 91} 92 93// Mips32/64 Instruction Format 94class InstSE<dag outs, dag ins, string asmstr, list<dag> pattern, 95 InstrItinClass itin, Format f, string opstr = ""> : 96 MipsInst<outs, ins, asmstr, pattern, itin, f>, PredicateControl { 97 let EncodingPredicates = [HasStdEnc]; 98 string BaseOpcode = opstr; 99 string Arch; 100} 101 102// Mips Pseudo Instructions Format 103class MipsPseudo<dag outs, dag ins, list<dag> pattern, 104 InstrItinClass itin = IIPseudo> : 105 MipsInst<outs, ins, "", pattern, itin, Pseudo> { 106 let isCodeGenOnly = 1; 107 let isPseudo = 1; 108} 109 110// Mips32/64 Pseudo Instruction Format 111class PseudoSE<dag outs, dag ins, list<dag> pattern, 112 InstrItinClass itin = IIPseudo> : 113 MipsPseudo<outs, ins, pattern, itin>, PredicateControl { 114 let EncodingPredicates = [HasStdEnc]; 115} 116 117// Pseudo-instructions for alternate assembly syntax (never used by codegen). 118// These are aliases that require C++ handling to convert to the target 119// instruction, while InstAliases can be handled directly by tblgen. 120class MipsAsmPseudoInst<dag outs, dag ins, string asmstr>: 121 MipsInst<outs, ins, asmstr, [], IIPseudo, Pseudo> { 122 let isPseudo = 1; 123 let Pattern = []; 124} 125//===----------------------------------------------------------------------===// 126// Format R instruction class in Mips : <|opcode|rs|rt|rd|shamt|funct|> 127//===----------------------------------------------------------------------===// 128 129class FR<bits<6> op, bits<6> _funct, dag outs, dag ins, string asmstr, 130 list<dag> pattern, InstrItinClass itin>: 131 InstSE<outs, ins, asmstr, pattern, itin, FrmR> 132{ 133 bits<5> rd; 134 bits<5> rs; 135 bits<5> rt; 136 bits<5> shamt; 137 bits<6> funct; 138 139 let Opcode = op; 140 let funct = _funct; 141 142 let Inst{25-21} = rs; 143 let Inst{20-16} = rt; 144 let Inst{15-11} = rd; 145 let Inst{10-6} = shamt; 146 let Inst{5-0} = funct; 147} 148 149//===----------------------------------------------------------------------===// 150// Format I instruction class in Mips : <|opcode|rs|rt|immediate|> 151//===----------------------------------------------------------------------===// 152 153class FI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern, 154 InstrItinClass itin>: InstSE<outs, ins, asmstr, pattern, itin, FrmI> 155{ 156 bits<5> rt; 157 bits<5> rs; 158 bits<16> imm16; 159 160 let Opcode = op; 161 162 let Inst{25-21} = rs; 163 let Inst{20-16} = rt; 164 let Inst{15-0} = imm16; 165} 166 167class BranchBase<bits<6> op, dag outs, dag ins, string asmstr, 168 list<dag> pattern, InstrItinClass itin>: 169 InstSE<outs, ins, asmstr, pattern, itin, FrmI> 170{ 171 bits<5> rs; 172 bits<5> rt; 173 bits<16> imm16; 174 175 let Opcode = op; 176 177 let Inst{25-21} = rs; 178 let Inst{20-16} = rt; 179 let Inst{15-0} = imm16; 180} 181 182//===----------------------------------------------------------------------===// 183// Format J instruction class in Mips : <|opcode|address|> 184//===----------------------------------------------------------------------===// 185 186class FJ<bits<6> op> : StdArch 187{ 188 bits<26> target; 189 190 bits<32> Inst; 191 192 let Inst{31-26} = op; 193 let Inst{25-0} = target; 194} 195 196//===----------------------------------------------------------------------===// 197// MFC instruction class in Mips : <|op|mf|rt|rd|0000000|sel|> 198//===----------------------------------------------------------------------===// 199class MFC3OP_FM<bits<6> op, bits<5> mfmt> 200{ 201 bits<5> rt; 202 bits<5> rd; 203 bits<3> sel; 204 205 bits<32> Inst; 206 207 let Inst{31-26} = op; 208 let Inst{25-21} = mfmt; 209 let Inst{20-16} = rt; 210 let Inst{15-11} = rd; 211 let Inst{10-3} = 0; 212 let Inst{2-0} = sel; 213} 214 215class ADD_FM<bits<6> op, bits<6> funct> : StdArch { 216 bits<5> rd; 217 bits<5> rs; 218 bits<5> rt; 219 220 bits<32> Inst; 221 222 let Inst{31-26} = op; 223 let Inst{25-21} = rs; 224 let Inst{20-16} = rt; 225 let Inst{15-11} = rd; 226 let Inst{10-6} = 0; 227 let Inst{5-0} = funct; 228} 229 230class ADDI_FM<bits<6> op> : StdArch { 231 bits<5> rs; 232 bits<5> rt; 233 bits<16> imm16; 234 235 bits<32> Inst; 236 237 let Inst{31-26} = op; 238 let Inst{25-21} = rs; 239 let Inst{20-16} = rt; 240 let Inst{15-0} = imm16; 241} 242 243class SRA_FM<bits<6> funct, bit rotate> : StdArch { 244 bits<5> rd; 245 bits<5> rt; 246 bits<5> shamt; 247 248 bits<32> Inst; 249 250 let Inst{31-26} = 0; 251 let Inst{25-22} = 0; 252 let Inst{21} = rotate; 253 let Inst{20-16} = rt; 254 let Inst{15-11} = rd; 255 let Inst{10-6} = shamt; 256 let Inst{5-0} = funct; 257} 258 259class SRLV_FM<bits<6> funct, bit rotate> : StdArch { 260 bits<5> rd; 261 bits<5> rt; 262 bits<5> rs; 263 264 bits<32> Inst; 265 266 let Inst{31-26} = 0; 267 let Inst{25-21} = rs; 268 let Inst{20-16} = rt; 269 let Inst{15-11} = rd; 270 let Inst{10-7} = 0; 271 let Inst{6} = rotate; 272 let Inst{5-0} = funct; 273} 274 275class BEQ_FM<bits<6> op> : StdArch { 276 bits<5> rs; 277 bits<5> rt; 278 bits<16> offset; 279 280 bits<32> Inst; 281 282 let Inst{31-26} = op; 283 let Inst{25-21} = rs; 284 let Inst{20-16} = rt; 285 let Inst{15-0} = offset; 286} 287 288class BGEZ_FM<bits<6> op, bits<5> funct> : StdArch { 289 bits<5> rs; 290 bits<16> offset; 291 292 bits<32> Inst; 293 294 let Inst{31-26} = op; 295 let Inst{25-21} = rs; 296 let Inst{20-16} = funct; 297 let Inst{15-0} = offset; 298} 299 300class BBIT_FM<bits<6> op> : StdArch { 301 bits<5> rs; 302 bits<5> p; 303 bits<16> offset; 304 305 bits<32> Inst; 306 307 let Inst{31-26} = op; 308 let Inst{25-21} = rs; 309 let Inst{20-16} = p; 310 let Inst{15-0} = offset; 311} 312 313class SLTI_FM<bits<6> op> : StdArch { 314 bits<5> rt; 315 bits<5> rs; 316 bits<16> imm16; 317 318 bits<32> Inst; 319 320 let Inst{31-26} = op; 321 let Inst{25-21} = rs; 322 let Inst{20-16} = rt; 323 let Inst{15-0} = imm16; 324} 325 326class MFLO_FM<bits<6> funct> : StdArch { 327 bits<5> rd; 328 329 bits<32> Inst; 330 331 let Inst{31-26} = 0; 332 let Inst{25-16} = 0; 333 let Inst{15-11} = rd; 334 let Inst{10-6} = 0; 335 let Inst{5-0} = funct; 336} 337 338class MTLO_FM<bits<6> funct> : StdArch { 339 bits<5> rs; 340 341 bits<32> Inst; 342 343 let Inst{31-26} = 0; 344 let Inst{25-21} = rs; 345 let Inst{20-6} = 0; 346 let Inst{5-0} = funct; 347} 348 349class SEB_FM<bits<5> funct, bits<6> funct2> : StdArch { 350 bits<5> rd; 351 bits<5> rt; 352 353 bits<32> Inst; 354 355 let Inst{31-26} = 0x1f; 356 let Inst{25-21} = 0; 357 let Inst{20-16} = rt; 358 let Inst{15-11} = rd; 359 let Inst{10-6} = funct; 360 let Inst{5-0} = funct2; 361} 362 363class CLO_FM<bits<6> funct> : StdArch { 364 bits<5> rd; 365 bits<5> rs; 366 bits<5> rt; 367 368 bits<32> Inst; 369 370 let Inst{31-26} = 0x1c; 371 let Inst{25-21} = rs; 372 let Inst{20-16} = rt; 373 let Inst{15-11} = rd; 374 let Inst{10-6} = 0; 375 let Inst{5-0} = funct; 376 let rt = rd; 377} 378 379class LUI_FM : StdArch { 380 bits<5> rt; 381 bits<16> imm16; 382 383 bits<32> Inst; 384 385 let Inst{31-26} = 0xf; 386 let Inst{25-21} = 0; 387 let Inst{20-16} = rt; 388 let Inst{15-0} = imm16; 389} 390 391class JALR_FM { 392 bits<5> rd; 393 bits<5> rs; 394 395 bits<32> Inst; 396 397 let Inst{31-26} = 0; 398 let Inst{25-21} = rs; 399 let Inst{20-16} = 0; 400 let Inst{15-11} = rd; 401 let Inst{10-6} = 0; 402 let Inst{5-0} = 9; 403} 404 405class BGEZAL_FM<bits<5> funct> : StdArch { 406 bits<5> rs; 407 bits<16> offset; 408 409 bits<32> Inst; 410 411 let Inst{31-26} = 1; 412 let Inst{25-21} = rs; 413 let Inst{20-16} = funct; 414 let Inst{15-0} = offset; 415} 416 417class SYNC_FM : StdArch { 418 bits<5> stype; 419 420 bits<32> Inst; 421 422 let Inst{31-26} = 0; 423 let Inst{10-6} = stype; 424 let Inst{5-0} = 0xf; 425} 426 427class SYNCI_FM : StdArch { 428 // Produced by the mem_simm16 address as reg << 16 | imm (see getMemEncoding). 429 bits<21> addr; 430 bits<5> rs = addr{20-16}; 431 bits<16> offset = addr{15-0}; 432 433 bits<32> Inst; 434 435 let Inst{31-26} = 0b000001; 436 let Inst{25-21} = rs; 437 let Inst{20-16} = 0b11111; 438 let Inst{15-0} = offset; 439} 440 441class MULT_FM<bits<6> op, bits<6> funct> : StdArch { 442 bits<5> rs; 443 bits<5> rt; 444 445 bits<32> Inst; 446 447 let Inst{31-26} = op; 448 let Inst{25-21} = rs; 449 let Inst{20-16} = rt; 450 let Inst{15-6} = 0; 451 let Inst{5-0} = funct; 452} 453 454class EXT_FM<bits<6> funct> : StdArch { 455 bits<5> rt; 456 bits<5> rs; 457 bits<5> pos; 458 bits<5> size; 459 460 bits<32> Inst; 461 462 let Inst{31-26} = 0x1f; 463 let Inst{25-21} = rs; 464 let Inst{20-16} = rt; 465 let Inst{15-11} = size; 466 let Inst{10-6} = pos; 467 let Inst{5-0} = funct; 468} 469 470class RDHWR_FM : StdArch { 471 bits<5> rt; 472 bits<5> rd; 473 474 bits<32> Inst; 475 476 let Inst{31-26} = 0x1f; 477 let Inst{25-21} = 0; 478 let Inst{20-16} = rt; 479 let Inst{15-11} = rd; 480 let Inst{10-6} = 0; 481 let Inst{5-0} = 0x3b; 482} 483 484class TEQ_FM<bits<6> funct> : StdArch { 485 bits<5> rs; 486 bits<5> rt; 487 bits<10> code_; 488 489 bits<32> Inst; 490 491 let Inst{31-26} = 0; 492 let Inst{25-21} = rs; 493 let Inst{20-16} = rt; 494 let Inst{15-6} = code_; 495 let Inst{5-0} = funct; 496} 497 498class TEQI_FM<bits<5> funct> : StdArch { 499 bits<5> rs; 500 bits<16> imm16; 501 502 bits<32> Inst; 503 504 let Inst{31-26} = 1; 505 let Inst{25-21} = rs; 506 let Inst{20-16} = funct; 507 let Inst{15-0} = imm16; 508} 509 510class WAIT_FM : StdArch { 511 bits<32> Inst; 512 513 let Inst{31-26} = 0x10; 514 let Inst{25} = 1; 515 let Inst{24-6} = 0; 516 let Inst{5-0} = 0x20; 517} 518 519class EXTS_FM<bits<6> funct> : StdArch { 520 bits<5> rt; 521 bits<5> rs; 522 bits<5> pos; 523 bits<5> lenm1; 524 525 bits<32> Inst; 526 527 let Inst{31-26} = 0x1c; 528 let Inst{25-21} = rs; 529 let Inst{20-16} = rt; 530 let Inst{15-11} = lenm1; 531 let Inst{10-6} = pos; 532 let Inst{5-0} = funct; 533} 534 535class MTMR_FM<bits<6> funct> : StdArch { 536 bits<5> rs; 537 538 bits<32> Inst; 539 540 let Inst{31-26} = 0x1c; 541 let Inst{25-21} = rs; 542 let Inst{20-6} = 0; 543 let Inst{5-0} = funct; 544} 545 546class POP_FM<bits<6> funct> : StdArch { 547 bits<5> rd; 548 bits<5> rs; 549 550 bits<32> Inst; 551 552 let Inst{31-26} = 0x1c; 553 let Inst{25-21} = rs; 554 let Inst{20-16} = 0; 555 let Inst{15-11} = rd; 556 let Inst{10-6} = 0; 557 let Inst{5-0} = funct; 558} 559 560class SEQ_FM<bits<6> funct> : StdArch { 561 bits<5> rd; 562 bits<5> rs; 563 bits<5> rt; 564 565 bits<32> Inst; 566 567 let Inst{31-26} = 0x1c; 568 let Inst{25-21} = rs; 569 let Inst{20-16} = rt; 570 let Inst{15-11} = rd; 571 let Inst{10-6} = 0; 572 let Inst{5-0} = funct; 573} 574 575class SEQI_FM<bits<6> funct> : StdArch { 576 bits<5> rs; 577 bits<5> rt; 578 bits<10> imm10; 579 580 bits<32> Inst; 581 582 let Inst{31-26} = 0x1c; 583 let Inst{25-21} = rs; 584 let Inst{20-16} = rt; 585 let Inst{15-6} = imm10; 586 let Inst{5-0} = funct; 587} 588 589//===----------------------------------------------------------------------===// 590// System calls format <op|code_|funct> 591//===----------------------------------------------------------------------===// 592 593class SYS_FM<bits<6> funct> : StdArch 594{ 595 bits<20> code_; 596 bits<32> Inst; 597 let Inst{31-26} = 0x0; 598 let Inst{25-6} = code_; 599 let Inst{5-0} = funct; 600} 601 602//===----------------------------------------------------------------------===// 603// Break instruction format <op|code_1|funct> 604//===----------------------------------------------------------------------===// 605 606class BRK_FM<bits<6> funct> : StdArch 607{ 608 bits<10> code_1; 609 bits<10> code_2; 610 bits<32> Inst; 611 let Inst{31-26} = 0x0; 612 let Inst{25-16} = code_1; 613 let Inst{15-6} = code_2; 614 let Inst{5-0} = funct; 615} 616 617//===----------------------------------------------------------------------===// 618// Exception return format <Cop0|1|0|funct> 619//===----------------------------------------------------------------------===// 620 621class ER_FM<bits<6> funct> : StdArch 622{ 623 bits<32> Inst; 624 let Inst{31-26} = 0x10; 625 let Inst{25} = 1; 626 let Inst{24-6} = 0; 627 let Inst{5-0} = funct; 628} 629 630 631//===----------------------------------------------------------------------===// 632// Enable/disable interrupt instruction format <Cop0|MFMC0|rt|12|0|sc|0|0> 633//===----------------------------------------------------------------------===// 634 635class EI_FM<bits<1> sc> : StdArch 636{ 637 bits<32> Inst; 638 bits<5> rt; 639 let Inst{31-26} = 0x10; 640 let Inst{25-21} = 0xb; 641 let Inst{20-16} = rt; 642 let Inst{15-11} = 0xc; 643 let Inst{10-6} = 0; 644 let Inst{5} = sc; 645 let Inst{4-0} = 0; 646} 647 648//===----------------------------------------------------------------------===// 649// 650// FLOATING POINT INSTRUCTION FORMATS 651// 652// opcode - operation code. 653// fs - src reg. 654// ft - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr). 655// fd - dst reg, only used on 3 regs instr. 656// fmt - double or single precision. 657// funct - combined with opcode field give us an operation code. 658// 659//===----------------------------------------------------------------------===// 660 661//===----------------------------------------------------------------------===// 662// Format FI instruction class in Mips : <|opcode|base|ft|immediate|> 663//===----------------------------------------------------------------------===// 664 665class FFI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern>: 666 InstSE<outs, ins, asmstr, pattern, NoItinerary, FrmFI> 667{ 668 bits<5> ft; 669 bits<5> base; 670 bits<16> imm16; 671 672 let Opcode = op; 673 674 let Inst{25-21} = base; 675 let Inst{20-16} = ft; 676 let Inst{15-0} = imm16; 677} 678 679class ADDS_FM<bits<6> funct, bits<5> fmt> : StdArch { 680 bits<5> fd; 681 bits<5> fs; 682 bits<5> ft; 683 684 bits<32> Inst; 685 686 let Inst{31-26} = 0x11; 687 let Inst{25-21} = fmt; 688 let Inst{20-16} = ft; 689 let Inst{15-11} = fs; 690 let Inst{10-6} = fd; 691 let Inst{5-0} = funct; 692} 693 694class ABSS_FM<bits<6> funct, bits<5> fmt> : StdArch { 695 bits<5> fd; 696 bits<5> fs; 697 698 bits<32> Inst; 699 700 let Inst{31-26} = 0x11; 701 let Inst{25-21} = fmt; 702 let Inst{20-16} = 0; 703 let Inst{15-11} = fs; 704 let Inst{10-6} = fd; 705 let Inst{5-0} = funct; 706} 707 708class MFC1_FM<bits<5> funct> : StdArch { 709 bits<5> rt; 710 bits<5> fs; 711 712 bits<32> Inst; 713 714 let Inst{31-26} = 0x11; 715 let Inst{25-21} = funct; 716 let Inst{20-16} = rt; 717 let Inst{15-11} = fs; 718 let Inst{10-0} = 0; 719} 720 721class LW_FM<bits<6> op> : StdArch { 722 bits<5> rt; 723 bits<21> addr; 724 725 bits<32> Inst; 726 727 let Inst{31-26} = op; 728 let Inst{25-21} = addr{20-16}; 729 let Inst{20-16} = rt; 730 let Inst{15-0} = addr{15-0}; 731} 732 733class MADDS_FM<bits<3> funct, bits<3> fmt> : StdArch { 734 bits<5> fd; 735 bits<5> fr; 736 bits<5> fs; 737 bits<5> ft; 738 739 bits<32> Inst; 740 741 let Inst{31-26} = 0x13; 742 let Inst{25-21} = fr; 743 let Inst{20-16} = ft; 744 let Inst{15-11} = fs; 745 let Inst{10-6} = fd; 746 let Inst{5-3} = funct; 747 let Inst{2-0} = fmt; 748} 749 750class LWXC1_FM<bits<6> funct> : StdArch { 751 bits<5> fd; 752 bits<5> base; 753 bits<5> index; 754 755 bits<32> Inst; 756 757 let Inst{31-26} = 0x13; 758 let Inst{25-21} = base; 759 let Inst{20-16} = index; 760 let Inst{15-11} = 0; 761 let Inst{10-6} = fd; 762 let Inst{5-0} = funct; 763} 764 765class SWXC1_FM<bits<6> funct> : StdArch { 766 bits<5> fs; 767 bits<5> base; 768 bits<5> index; 769 770 bits<32> Inst; 771 772 let Inst{31-26} = 0x13; 773 let Inst{25-21} = base; 774 let Inst{20-16} = index; 775 let Inst{15-11} = fs; 776 let Inst{10-6} = 0; 777 let Inst{5-0} = funct; 778} 779 780class BC1F_FM<bit nd, bit tf> : StdArch { 781 bits<3> fcc; 782 bits<16> offset; 783 784 bits<32> Inst; 785 786 let Inst{31-26} = 0x11; 787 let Inst{25-21} = 0x8; 788 let Inst{20-18} = fcc; 789 let Inst{17} = nd; 790 let Inst{16} = tf; 791 let Inst{15-0} = offset; 792} 793 794class CEQS_FM<bits<5> fmt> : StdArch { 795 bits<5> fs; 796 bits<5> ft; 797 bits<4> cond; 798 799 bits<32> Inst; 800 801 let Inst{31-26} = 0x11; 802 let Inst{25-21} = fmt; 803 let Inst{20-16} = ft; 804 let Inst{15-11} = fs; 805 let Inst{10-8} = 0; // cc 806 let Inst{7-4} = 0x3; 807 let Inst{3-0} = cond; 808} 809 810class C_COND_FM<bits<5> fmt, bits<4> c> : CEQS_FM<fmt> { 811 let cond = c; 812} 813 814class CMov_I_F_FM<bits<6> funct, bits<5> fmt> : StdArch { 815 bits<5> fd; 816 bits<5> fs; 817 bits<5> rt; 818 819 bits<32> Inst; 820 821 let Inst{31-26} = 0x11; 822 let Inst{25-21} = fmt; 823 let Inst{20-16} = rt; 824 let Inst{15-11} = fs; 825 let Inst{10-6} = fd; 826 let Inst{5-0} = funct; 827} 828 829class CMov_F_I_FM<bit tf> : StdArch { 830 bits<5> rd; 831 bits<5> rs; 832 bits<3> fcc; 833 834 bits<32> Inst; 835 836 let Inst{31-26} = 0; 837 let Inst{25-21} = rs; 838 let Inst{20-18} = fcc; 839 let Inst{17} = 0; 840 let Inst{16} = tf; 841 let Inst{15-11} = rd; 842 let Inst{10-6} = 0; 843 let Inst{5-0} = 1; 844} 845 846class CMov_F_F_FM<bits<5> fmt, bit tf> : StdArch { 847 bits<5> fd; 848 bits<5> fs; 849 bits<3> fcc; 850 851 bits<32> Inst; 852 853 let Inst{31-26} = 0x11; 854 let Inst{25-21} = fmt; 855 let Inst{20-18} = fcc; 856 let Inst{17} = 0; 857 let Inst{16} = tf; 858 let Inst{15-11} = fs; 859 let Inst{10-6} = fd; 860 let Inst{5-0} = 0x11; 861} 862 863class BARRIER_FM<bits<5> op> : StdArch { 864 bits<32> Inst; 865 866 let Inst{31-26} = 0; // SPECIAL 867 let Inst{25-21} = 0; 868 let Inst{20-16} = 0; // rt = 0 869 let Inst{15-11} = 0; // rd = 0 870 let Inst{10-6} = op; // Operation 871 let Inst{5-0} = 0; // SLL 872} 873 874class SDBBP_FM : StdArch { 875 bits<20> code_; 876 877 bits<32> Inst; 878 879 let Inst{31-26} = 0b011100; // SPECIAL2 880 let Inst{25-6} = code_; 881 let Inst{5-0} = 0b111111; // SDBBP 882} 883 884class JR_HB_FM<bits<6> op> : StdArch{ 885 bits<5> rs; 886 887 bits<32> Inst; 888 889 let Inst{31-26} = 0; // SPECIAL 890 let Inst{25-21} = rs; 891 let Inst{20-11} = 0; 892 let Inst{10} = 1; 893 let Inst{9-6} = 0; 894 let Inst{5-0} = op; 895} 896 897class JALR_HB_FM<bits<6> op> : StdArch { 898 bits<5> rd; 899 bits<5> rs; 900 901 bits<32> Inst; 902 903 let Inst{31-26} = 0; // SPECIAL 904 let Inst{25-21} = rs; 905 let Inst{20-16} = 0; 906 let Inst{15-11} = rd; 907 let Inst{10} = 1; 908 let Inst{9-6} = 0; 909 let Inst{5-0} = op; 910} 911 912class COP0_TLB_FM<bits<6> op> : StdArch { 913 bits<32> Inst; 914 915 let Inst{31-26} = 0x10; // COP0 916 let Inst{25} = 1; // CO 917 let Inst{24-6} = 0; 918 let Inst{5-0} = op; // Operation 919} 920 921class CACHEOP_FM<bits<6> op> : StdArch { 922 bits<21> addr; 923 bits<5> hint; 924 bits<5> base = addr{20-16}; 925 bits<16> offset = addr{15-0}; 926 927 bits<32> Inst; 928 929 let Inst{31-26} = op; 930 let Inst{25-21} = base; 931 let Inst{20-16} = hint; 932 let Inst{15-0} = offset; 933} 934