1 //===-- MipsSERegisterInfo.cpp - MIPS32/64 Register Information -== -------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the MIPS32/64 implementation of the TargetRegisterInfo
11 // class.
12 //
13 //===----------------------------------------------------------------------===//
14
15 #include "MipsSERegisterInfo.h"
16 #include "Mips.h"
17 #include "MipsAnalyzeImmediate.h"
18 #include "MipsMachineFunction.h"
19 #include "MipsSEInstrInfo.h"
20 #include "MipsSubtarget.h"
21 #include "MipsTargetMachine.h"
22 #include "llvm/ADT/BitVector.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/IR/Constants.h"
29 #include "llvm/IR/DebugInfo.h"
30 #include "llvm/IR/Function.h"
31 #include "llvm/IR/Type.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/raw_ostream.h"
36 #include "llvm/Target/TargetFrameLowering.h"
37 #include "llvm/Target/TargetInstrInfo.h"
38 #include "llvm/Target/TargetMachine.h"
39 #include "llvm/Target/TargetOptions.h"
40
41 using namespace llvm;
42
43 #define DEBUG_TYPE "mips-reg-info"
44
MipsSERegisterInfo()45 MipsSERegisterInfo::MipsSERegisterInfo() : MipsRegisterInfo() {}
46
47 bool MipsSERegisterInfo::
requiresRegisterScavenging(const MachineFunction & MF) const48 requiresRegisterScavenging(const MachineFunction &MF) const {
49 return true;
50 }
51
52 bool MipsSERegisterInfo::
requiresFrameIndexScavenging(const MachineFunction & MF) const53 requiresFrameIndexScavenging(const MachineFunction &MF) const {
54 return true;
55 }
56
57 const TargetRegisterClass *
intRegClass(unsigned Size) const58 MipsSERegisterInfo::intRegClass(unsigned Size) const {
59 if (Size == 4)
60 return &Mips::GPR32RegClass;
61
62 assert(Size == 8);
63 return &Mips::GPR64RegClass;
64 }
65
66 /// Get the size of the offset supported by the given load/store.
67 /// The result includes the effects of any scale factors applied to the
68 /// instruction immediate.
getLoadStoreOffsetSizeInBits(const unsigned Opcode)69 static inline unsigned getLoadStoreOffsetSizeInBits(const unsigned Opcode) {
70 switch (Opcode) {
71 case Mips::LD_B:
72 case Mips::ST_B:
73 return 10;
74 case Mips::LD_H:
75 case Mips::ST_H:
76 return 10 + 1 /* scale factor */;
77 case Mips::LD_W:
78 case Mips::ST_W:
79 return 10 + 2 /* scale factor */;
80 case Mips::LD_D:
81 case Mips::ST_D:
82 return 10 + 3 /* scale factor */;
83 default:
84 return 16;
85 }
86 }
87
88 /// Get the scale factor applied to the immediate in the given load/store.
getLoadStoreOffsetAlign(const unsigned Opcode)89 static inline unsigned getLoadStoreOffsetAlign(const unsigned Opcode) {
90 switch (Opcode) {
91 case Mips::LD_H:
92 case Mips::ST_H:
93 return 2;
94 case Mips::LD_W:
95 case Mips::ST_W:
96 return 4;
97 case Mips::LD_D:
98 case Mips::ST_D:
99 return 8;
100 default:
101 return 1;
102 }
103 }
104
eliminateFI(MachineBasicBlock::iterator II,unsigned OpNo,int FrameIndex,uint64_t StackSize,int64_t SPOffset) const105 void MipsSERegisterInfo::eliminateFI(MachineBasicBlock::iterator II,
106 unsigned OpNo, int FrameIndex,
107 uint64_t StackSize,
108 int64_t SPOffset) const {
109 MachineInstr &MI = *II;
110 MachineFunction &MF = *MI.getParent()->getParent();
111 MachineFrameInfo *MFI = MF.getFrameInfo();
112 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
113 bool isN64 =
114 static_cast<const MipsTargetMachine &>(MF.getTarget()).getABI().IsN64();
115
116 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
117 int MinCSFI = 0;
118 int MaxCSFI = -1;
119
120 if (CSI.size()) {
121 MinCSFI = CSI[0].getFrameIdx();
122 MaxCSFI = CSI[CSI.size() - 1].getFrameIdx();
123 }
124
125 bool EhDataRegFI = MipsFI->isEhDataRegFI(FrameIndex);
126
127 // The following stack frame objects are always referenced relative to $sp:
128 // 1. Outgoing arguments.
129 // 2. Pointer to dynamically allocated stack space.
130 // 3. Locations for callee-saved registers.
131 // 4. Locations for eh data registers.
132 // Everything else is referenced relative to whatever register
133 // getFrameRegister() returns.
134 unsigned FrameReg;
135
136 if ((FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI) || EhDataRegFI)
137 FrameReg = isN64 ? Mips::SP_64 : Mips::SP;
138 else
139 FrameReg = getFrameRegister(MF);
140
141 // Calculate final offset.
142 // - There is no need to change the offset if the frame object is one of the
143 // following: an outgoing argument, pointer to a dynamically allocated
144 // stack space or a $gp restore location,
145 // - If the frame object is any of the following, its offset must be adjusted
146 // by adding the size of the stack:
147 // incoming argument, callee-saved register location or local variable.
148 bool IsKill = false;
149 int64_t Offset;
150
151 Offset = SPOffset + (int64_t)StackSize;
152 Offset += MI.getOperand(OpNo + 1).getImm();
153
154 DEBUG(errs() << "Offset : " << Offset << "\n" << "<--------->\n");
155
156 if (!MI.isDebugValue()) {
157 // Make sure Offset fits within the field available.
158 // For MSA instructions, this is a 10-bit signed immediate (scaled by
159 // element size), otherwise it is a 16-bit signed immediate.
160 unsigned OffsetBitSize = getLoadStoreOffsetSizeInBits(MI.getOpcode());
161 unsigned OffsetAlign = getLoadStoreOffsetAlign(MI.getOpcode());
162
163 if (OffsetBitSize < 16 && isInt<16>(Offset) &&
164 (!isIntN(OffsetBitSize, Offset) ||
165 OffsetToAlignment(Offset, OffsetAlign) != 0)) {
166 // If we have an offset that needs to fit into a signed n-bit immediate
167 // (where n < 16) and doesn't, but does fit into 16-bits then use an ADDiu
168 MachineBasicBlock &MBB = *MI.getParent();
169 DebugLoc DL = II->getDebugLoc();
170 unsigned ADDiu = isN64 ? Mips::DADDiu : Mips::ADDiu;
171 const TargetRegisterClass *RC =
172 isN64 ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
173 MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
174 unsigned Reg = RegInfo.createVirtualRegister(RC);
175 const MipsSEInstrInfo &TII =
176 *static_cast<const MipsSEInstrInfo *>(
177 MBB.getParent()->getSubtarget().getInstrInfo());
178 BuildMI(MBB, II, DL, TII.get(ADDiu), Reg).addReg(FrameReg).addImm(Offset);
179
180 FrameReg = Reg;
181 Offset = 0;
182 IsKill = true;
183 } else if (!isInt<16>(Offset)) {
184 // Otherwise split the offset into 16-bit pieces and add it in multiple
185 // instructions.
186 MachineBasicBlock &MBB = *MI.getParent();
187 DebugLoc DL = II->getDebugLoc();
188 unsigned ADDu = isN64 ? Mips::DADDu : Mips::ADDu;
189 unsigned NewImm = 0;
190 const MipsSEInstrInfo &TII =
191 *static_cast<const MipsSEInstrInfo *>(
192 MBB.getParent()->getSubtarget().getInstrInfo());
193 unsigned Reg = TII.loadImmediate(Offset, MBB, II, DL,
194 OffsetBitSize == 16 ? &NewImm : nullptr);
195 BuildMI(MBB, II, DL, TII.get(ADDu), Reg).addReg(FrameReg)
196 .addReg(Reg, RegState::Kill);
197
198 FrameReg = Reg;
199 Offset = SignExtend64<16>(NewImm);
200 IsKill = true;
201 }
202 }
203
204 MI.getOperand(OpNo).ChangeToRegister(FrameReg, false, false, IsKill);
205 MI.getOperand(OpNo + 1).ChangeToImmediate(Offset);
206 }
207