1 //===-- SIISelLowering.h - SI DAG Lowering Interface ------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 /// \file 11 /// \brief SI DAG Lowering interface definition 12 // 13 //===----------------------------------------------------------------------===// 14 15 #ifndef LLVM_LIB_TARGET_R600_SIISELLOWERING_H 16 #define LLVM_LIB_TARGET_R600_SIISELLOWERING_H 17 18 #include "AMDGPUISelLowering.h" 19 #include "SIInstrInfo.h" 20 21 namespace llvm { 22 23 class SITargetLowering : public AMDGPUTargetLowering { 24 SDValue LowerParameter(SelectionDAG &DAG, EVT VT, EVT MemVT, SDLoc DL, 25 SDValue Chain, unsigned Offset, bool Signed) const; 26 SDValue LowerSampleIntrinsic(unsigned Opcode, const SDValue &Op, 27 SelectionDAG &DAG) const; 28 SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op, 29 SelectionDAG &DAG) const override; 30 31 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 32 SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const; 33 SDValue LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const; 34 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const; 35 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const; 36 SDValue LowerFastFDIV(SDValue Op, SelectionDAG &DAG) const; 37 SDValue LowerFDIV32(SDValue Op, SelectionDAG &DAG) const; 38 SDValue LowerFDIV64(SDValue Op, SelectionDAG &DAG) const; 39 SDValue LowerFDIV(SDValue Op, SelectionDAG &DAG) const; 40 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG, bool Signed) const; 41 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const; 42 SDValue LowerTrig(SDValue Op, SelectionDAG &DAG) const; 43 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const; 44 45 void adjustWritemask(MachineSDNode *&N, SelectionDAG &DAG) const; 46 47 SDValue performUCharToFloatCombine(SDNode *N, 48 DAGCombinerInfo &DCI) const; 49 SDValue performSHLPtrCombine(SDNode *N, 50 unsigned AS, 51 DAGCombinerInfo &DCI) const; 52 SDValue performAndCombine(SDNode *N, DAGCombinerInfo &DCI) const; 53 SDValue performOrCombine(SDNode *N, DAGCombinerInfo &DCI) const; 54 SDValue performClassCombine(SDNode *N, DAGCombinerInfo &DCI) const; 55 56 SDValue performMin3Max3Combine(SDNode *N, DAGCombinerInfo &DCI) const; 57 SDValue performSetCCCombine(SDNode *N, DAGCombinerInfo &DCI) const; 58 59 public: 60 SITargetLowering(TargetMachine &tm, const AMDGPUSubtarget &STI); 61 62 bool isShuffleMaskLegal(const SmallVectorImpl<int> &/*Mask*/, 63 EVT /*VT*/) const override; 64 65 bool isLegalAddressingMode(const AddrMode &AM, 66 Type *Ty) const override; 67 68 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, 69 unsigned Align, 70 bool *IsFast) const override; 71 72 EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, 73 unsigned SrcAlign, bool IsMemset, 74 bool ZeroMemset, 75 bool MemcpyStrSrc, 76 MachineFunction &MF) const override; 77 78 TargetLoweringBase::LegalizeTypeAction 79 getPreferredVectorAction(EVT VT) const override; 80 81 bool shouldConvertConstantLoadToIntImm(const APInt &Imm, 82 Type *Ty) const override; 83 84 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, 85 bool isVarArg, 86 const SmallVectorImpl<ISD::InputArg> &Ins, 87 SDLoc DL, SelectionDAG &DAG, 88 SmallVectorImpl<SDValue> &InVals) const override; 89 90 MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr * MI, 91 MachineBasicBlock * BB) const override; 92 bool enableAggressiveFMAFusion(EVT VT) const override; 93 EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override; 94 MVT getScalarShiftAmountTy(EVT VT) const override; 95 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override; 96 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 97 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; 98 SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const override; 99 void AdjustInstrPostInstrSelection(MachineInstr *MI, 100 SDNode *Node) const override; 101 102 int32_t analyzeImmediate(const SDNode *N) const; 103 SDValue CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC, 104 unsigned Reg, EVT VT) const override; 105 void legalizeTargetIndependentNode(SDNode *Node, SelectionDAG &DAG) const; 106 107 MachineSDNode *wrapAddr64Rsrc(SelectionDAG &DAG, SDLoc DL, SDValue Ptr) const; 108 MachineSDNode *buildRSRC(SelectionDAG &DAG, 109 SDLoc DL, 110 SDValue Ptr, 111 uint32_t RsrcDword1, 112 uint64_t RsrcDword2And3) const; 113 MachineSDNode *buildScratchRSRC(SelectionDAG &DAG, 114 SDLoc DL, 115 SDValue Ptr) const; 116 117 std::pair<unsigned, const TargetRegisterClass *> getRegForInlineAsmConstraint( 118 const TargetRegisterInfo *TRI, 119 const std::string &Constraint, MVT VT) const override; 120 }; 121 122 } // End namespace llvm 123 124 #endif 125