1//===-- SIInstrFormats.td - SI Instruction Encodings ----------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// SI Instruction format definitions. 11// 12//===----------------------------------------------------------------------===// 13 14class InstSI <dag outs, dag ins, string asm, list<dag> pattern> : 15 AMDGPUInst<outs, ins, asm, pattern>, PredicateControl { 16 17 field bits<1> VM_CNT = 0; 18 field bits<1> EXP_CNT = 0; 19 field bits<1> LGKM_CNT = 0; 20 21 field bits<1> SALU = 0; 22 field bits<1> VALU = 0; 23 24 field bits<1> SOP1 = 0; 25 field bits<1> SOP2 = 0; 26 field bits<1> SOPC = 0; 27 field bits<1> SOPK = 0; 28 field bits<1> SOPP = 0; 29 30 field bits<1> VOP1 = 0; 31 field bits<1> VOP2 = 0; 32 field bits<1> VOP3 = 0; 33 field bits<1> VOPC = 0; 34 35 field bits<1> MUBUF = 0; 36 field bits<1> MTBUF = 0; 37 field bits<1> SMRD = 0; 38 field bits<1> DS = 0; 39 field bits<1> MIMG = 0; 40 field bits<1> FLAT = 0; 41 field bits<1> WQM = 0; 42 43 // These need to be kept in sync with the enum in SIInstrFlags. 44 let TSFlags{0} = VM_CNT; 45 let TSFlags{1} = EXP_CNT; 46 let TSFlags{2} = LGKM_CNT; 47 48 let TSFlags{3} = SALU; 49 let TSFlags{4} = VALU; 50 51 let TSFlags{5} = SOP1; 52 let TSFlags{6} = SOP2; 53 let TSFlags{7} = SOPC; 54 let TSFlags{8} = SOPK; 55 let TSFlags{9} = SOPP; 56 57 let TSFlags{10} = VOP1; 58 let TSFlags{11} = VOP2; 59 let TSFlags{12} = VOP3; 60 let TSFlags{13} = VOPC; 61 62 let TSFlags{14} = MUBUF; 63 let TSFlags{15} = MTBUF; 64 let TSFlags{16} = SMRD; 65 let TSFlags{17} = DS; 66 let TSFlags{18} = MIMG; 67 let TSFlags{19} = FLAT; 68 let TSFlags{20} = WQM; 69 70 // Most instructions require adjustments after selection to satisfy 71 // operand requirements. 72 let hasPostISelHook = 1; 73 let SchedRW = [Write32Bit]; 74} 75 76class Enc32 { 77 field bits<32> Inst; 78 int Size = 4; 79} 80 81class Enc64 { 82 field bits<64> Inst; 83 int Size = 8; 84} 85 86class VOPDstOperand <RegisterClass rc> : RegisterOperand <rc, "printVOPDst">; 87def VOPDstVCC : VOPDstOperand <VCCReg>; 88 89let Uses = [EXEC] in { 90 91class VOPAnyCommon <dag outs, dag ins, string asm, list<dag> pattern> : 92 InstSI <outs, ins, asm, pattern> { 93 94 let mayLoad = 0; 95 let mayStore = 0; 96 let hasSideEffects = 0; 97 let UseNamedOperandTable = 1; 98 let VALU = 1; 99} 100 101class VOPCCommon <dag ins, string asm, list<dag> pattern> : 102 VOPAnyCommon <(outs VOPDstVCC:$dst), ins, asm, pattern> { 103 104 let DisableEncoding = "$dst"; 105 let VOPC = 1; 106 let Size = 4; 107} 108 109class VOP1Common <dag outs, dag ins, string asm, list<dag> pattern> : 110 VOPAnyCommon <outs, ins, asm, pattern> { 111 112 let VOP1 = 1; 113 let Size = 4; 114} 115 116class VOP2Common <dag outs, dag ins, string asm, list<dag> pattern> : 117 VOPAnyCommon <outs, ins, asm, pattern> { 118 119 let VOP2 = 1; 120 let Size = 4; 121} 122 123class VOP3Common <dag outs, dag ins, string asm, list<dag> pattern> : 124 VOPAnyCommon <outs, ins, asm, pattern> { 125 126 // Using complex patterns gives VOP3 patterns a very high complexity rating, 127 // but standalone patterns are almost always prefered, so we need to adjust the 128 // priority lower. The goal is to use a high number to reduce complexity to 129 // zero (or less than zero). 130 let AddedComplexity = -1000; 131 132 let VOP3 = 1; 133 let VALU = 1; 134 135 let AsmMatchConverter = "cvtVOP3"; 136 let isCodeGenOnly = 0; 137 138 int Size = 8; 139} 140 141} // End Uses = [EXEC] 142 143//===----------------------------------------------------------------------===// 144// Scalar operations 145//===----------------------------------------------------------------------===// 146 147class SOP1e <bits<8> op> : Enc32 { 148 bits<7> sdst; 149 bits<8> ssrc0; 150 151 let Inst{7-0} = ssrc0; 152 let Inst{15-8} = op; 153 let Inst{22-16} = sdst; 154 let Inst{31-23} = 0x17d; //encoding; 155} 156 157class SOP2e <bits<7> op> : Enc32 { 158 bits<7> sdst; 159 bits<8> ssrc0; 160 bits<8> ssrc1; 161 162 let Inst{7-0} = ssrc0; 163 let Inst{15-8} = ssrc1; 164 let Inst{22-16} = sdst; 165 let Inst{29-23} = op; 166 let Inst{31-30} = 0x2; // encoding 167} 168 169class SOPCe <bits<7> op> : Enc32 { 170 bits<8> ssrc0; 171 bits<8> ssrc1; 172 173 let Inst{7-0} = ssrc0; 174 let Inst{15-8} = ssrc1; 175 let Inst{22-16} = op; 176 let Inst{31-23} = 0x17e; 177} 178 179class SOPKe <bits<5> op> : Enc32 { 180 bits <7> sdst; 181 bits <16> simm16; 182 183 let Inst{15-0} = simm16; 184 let Inst{22-16} = sdst; 185 let Inst{27-23} = op; 186 let Inst{31-28} = 0xb; //encoding 187} 188 189class SOPK64e <bits<5> op> : Enc64 { 190 bits <7> sdst = 0; 191 bits <16> simm16; 192 bits <32> imm; 193 194 let Inst{15-0} = simm16; 195 let Inst{22-16} = sdst; 196 let Inst{27-23} = op; 197 let Inst{31-28} = 0xb; 198 199 let Inst{63-32} = imm; 200} 201 202class SOPPe <bits<7> op> : Enc32 { 203 bits <16> simm16; 204 205 let Inst{15-0} = simm16; 206 let Inst{22-16} = op; 207 let Inst{31-23} = 0x17f; // encoding 208} 209 210class SMRDe <bits<5> op, bits<1> imm> : Enc32 { 211 bits<7> sdst; 212 bits<7> sbase; 213 bits<8> offset; 214 215 let Inst{7-0} = offset; 216 let Inst{8} = imm; 217 let Inst{14-9} = sbase{6-1}; 218 let Inst{21-15} = sdst; 219 let Inst{26-22} = op; 220 let Inst{31-27} = 0x18; //encoding 221} 222 223let SchedRW = [WriteSALU] in { 224class SOP1 <dag outs, dag ins, string asm, list<dag> pattern> : 225 InstSI<outs, ins, asm, pattern> { 226 let mayLoad = 0; 227 let mayStore = 0; 228 let hasSideEffects = 0; 229 let isCodeGenOnly = 0; 230 let SALU = 1; 231 let SOP1 = 1; 232} 233 234class SOP2 <dag outs, dag ins, string asm, list<dag> pattern> : 235 InstSI <outs, ins, asm, pattern> { 236 237 let mayLoad = 0; 238 let mayStore = 0; 239 let hasSideEffects = 0; 240 let isCodeGenOnly = 0; 241 let SALU = 1; 242 let SOP2 = 1; 243 244 let UseNamedOperandTable = 1; 245} 246 247class SOPC <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> : 248 InstSI<outs, ins, asm, pattern>, SOPCe <op> { 249 250 let DisableEncoding = "$dst"; 251 let mayLoad = 0; 252 let mayStore = 0; 253 let hasSideEffects = 0; 254 let SALU = 1; 255 let SOPC = 1; 256 let isCodeGenOnly = 0; 257 258 let UseNamedOperandTable = 1; 259} 260 261class SOPK <dag outs, dag ins, string asm, list<dag> pattern> : 262 InstSI <outs, ins , asm, pattern> { 263 264 let mayLoad = 0; 265 let mayStore = 0; 266 let hasSideEffects = 0; 267 let SALU = 1; 268 let SOPK = 1; 269 270 let UseNamedOperandTable = 1; 271} 272 273class SOPP <bits<7> op, dag ins, string asm, list<dag> pattern = []> : 274 InstSI <(outs), ins, asm, pattern >, SOPPe <op> { 275 276 let mayLoad = 0; 277 let mayStore = 0; 278 let hasSideEffects = 0; 279 let SALU = 1; 280 let SOPP = 1; 281 282 let UseNamedOperandTable = 1; 283} 284 285} // let SchedRW = [WriteSALU] 286 287class SMRD <dag outs, dag ins, string asm, list<dag> pattern> : 288 InstSI<outs, ins, asm, pattern> { 289 290 let LGKM_CNT = 1; 291 let SMRD = 1; 292 let mayStore = 0; 293 let mayLoad = 1; 294 let hasSideEffects = 0; 295 let UseNamedOperandTable = 1; 296 let SchedRW = [WriteSMEM]; 297} 298 299//===----------------------------------------------------------------------===// 300// Vector ALU operations 301//===----------------------------------------------------------------------===// 302 303class VOP1e <bits<8> op> : Enc32 { 304 bits<8> vdst; 305 bits<9> src0; 306 307 let Inst{8-0} = src0; 308 let Inst{16-9} = op; 309 let Inst{24-17} = vdst; 310 let Inst{31-25} = 0x3f; //encoding 311} 312 313class VOP2e <bits<6> op> : Enc32 { 314 bits<8> vdst; 315 bits<9> src0; 316 bits<8> src1; 317 318 let Inst{8-0} = src0; 319 let Inst{16-9} = src1; 320 let Inst{24-17} = vdst; 321 let Inst{30-25} = op; 322 let Inst{31} = 0x0; //encoding 323} 324 325class VOP2_MADKe <bits<6> op> : Enc64 { 326 327 bits<8> vdst; 328 bits<9> src0; 329 bits<8> vsrc1; 330 bits<32> src2; 331 332 let Inst{8-0} = src0; 333 let Inst{16-9} = vsrc1; 334 let Inst{24-17} = vdst; 335 let Inst{30-25} = op; 336 let Inst{31} = 0x0; // encoding 337 let Inst{63-32} = src2; 338} 339 340class VOP3e <bits<9> op> : Enc64 { 341 bits<8> vdst; 342 bits<2> src0_modifiers; 343 bits<9> src0; 344 bits<2> src1_modifiers; 345 bits<9> src1; 346 bits<2> src2_modifiers; 347 bits<9> src2; 348 bits<1> clamp; 349 bits<2> omod; 350 351 let Inst{7-0} = vdst; 352 let Inst{8} = src0_modifiers{1}; 353 let Inst{9} = src1_modifiers{1}; 354 let Inst{10} = src2_modifiers{1}; 355 let Inst{11} = clamp; 356 let Inst{25-17} = op; 357 let Inst{31-26} = 0x34; //encoding 358 let Inst{40-32} = src0; 359 let Inst{49-41} = src1; 360 let Inst{58-50} = src2; 361 let Inst{60-59} = omod; 362 let Inst{61} = src0_modifiers{0}; 363 let Inst{62} = src1_modifiers{0}; 364 let Inst{63} = src2_modifiers{0}; 365} 366 367class VOP3be <bits<9> op> : Enc64 { 368 bits<8> vdst; 369 bits<2> src0_modifiers; 370 bits<9> src0; 371 bits<2> src1_modifiers; 372 bits<9> src1; 373 bits<2> src2_modifiers; 374 bits<9> src2; 375 bits<7> sdst; 376 bits<2> omod; 377 378 let Inst{7-0} = vdst; 379 let Inst{14-8} = sdst; 380 let Inst{25-17} = op; 381 let Inst{31-26} = 0x34; //encoding 382 let Inst{40-32} = src0; 383 let Inst{49-41} = src1; 384 let Inst{58-50} = src2; 385 let Inst{60-59} = omod; 386 let Inst{61} = src0_modifiers{0}; 387 let Inst{62} = src1_modifiers{0}; 388 let Inst{63} = src2_modifiers{0}; 389} 390 391class VOPCe <bits<8> op> : Enc32 { 392 bits<9> src0; 393 bits<8> vsrc1; 394 395 let Inst{8-0} = src0; 396 let Inst{16-9} = vsrc1; 397 let Inst{24-17} = op; 398 let Inst{31-25} = 0x3e; 399} 400 401class VINTRPe <bits<2> op> : Enc32 { 402 bits<8> vdst; 403 bits<8> vsrc; 404 bits<2> attrchan; 405 bits<6> attr; 406 407 let Inst{7-0} = vsrc; 408 let Inst{9-8} = attrchan; 409 let Inst{15-10} = attr; 410 let Inst{17-16} = op; 411 let Inst{25-18} = vdst; 412 let Inst{31-26} = 0x32; // encoding 413} 414 415class DSe <bits<8> op> : Enc64 { 416 bits<8> vdst; 417 bits<1> gds; 418 bits<8> addr; 419 bits<8> data0; 420 bits<8> data1; 421 bits<8> offset0; 422 bits<8> offset1; 423 424 let Inst{7-0} = offset0; 425 let Inst{15-8} = offset1; 426 let Inst{17} = gds; 427 let Inst{25-18} = op; 428 let Inst{31-26} = 0x36; //encoding 429 let Inst{39-32} = addr; 430 let Inst{47-40} = data0; 431 let Inst{55-48} = data1; 432 let Inst{63-56} = vdst; 433} 434 435class MUBUFe <bits<7> op> : Enc64 { 436 bits<12> offset; 437 bits<1> offen; 438 bits<1> idxen; 439 bits<1> glc; 440 bits<1> addr64; 441 bits<1> lds; 442 bits<8> vaddr; 443 bits<8> vdata; 444 bits<7> srsrc; 445 bits<1> slc; 446 bits<1> tfe; 447 bits<8> soffset; 448 449 let Inst{11-0} = offset; 450 let Inst{12} = offen; 451 let Inst{13} = idxen; 452 let Inst{14} = glc; 453 let Inst{15} = addr64; 454 let Inst{16} = lds; 455 let Inst{24-18} = op; 456 let Inst{31-26} = 0x38; //encoding 457 let Inst{39-32} = vaddr; 458 let Inst{47-40} = vdata; 459 let Inst{52-48} = srsrc{6-2}; 460 let Inst{54} = slc; 461 let Inst{55} = tfe; 462 let Inst{63-56} = soffset; 463} 464 465class MTBUFe <bits<3> op> : Enc64 { 466 bits<8> vdata; 467 bits<12> offset; 468 bits<1> offen; 469 bits<1> idxen; 470 bits<1> glc; 471 bits<1> addr64; 472 bits<4> dfmt; 473 bits<3> nfmt; 474 bits<8> vaddr; 475 bits<7> srsrc; 476 bits<1> slc; 477 bits<1> tfe; 478 bits<8> soffset; 479 480 let Inst{11-0} = offset; 481 let Inst{12} = offen; 482 let Inst{13} = idxen; 483 let Inst{14} = glc; 484 let Inst{15} = addr64; 485 let Inst{18-16} = op; 486 let Inst{22-19} = dfmt; 487 let Inst{25-23} = nfmt; 488 let Inst{31-26} = 0x3a; //encoding 489 let Inst{39-32} = vaddr; 490 let Inst{47-40} = vdata; 491 let Inst{52-48} = srsrc{6-2}; 492 let Inst{54} = slc; 493 let Inst{55} = tfe; 494 let Inst{63-56} = soffset; 495} 496 497class MIMGe <bits<7> op> : Enc64 { 498 bits<8> vdata; 499 bits<4> dmask; 500 bits<1> unorm; 501 bits<1> glc; 502 bits<1> da; 503 bits<1> r128; 504 bits<1> tfe; 505 bits<1> lwe; 506 bits<1> slc; 507 bits<8> vaddr; 508 bits<7> srsrc; 509 bits<7> ssamp; 510 511 let Inst{11-8} = dmask; 512 let Inst{12} = unorm; 513 let Inst{13} = glc; 514 let Inst{14} = da; 515 let Inst{15} = r128; 516 let Inst{16} = tfe; 517 let Inst{17} = lwe; 518 let Inst{24-18} = op; 519 let Inst{25} = slc; 520 let Inst{31-26} = 0x3c; 521 let Inst{39-32} = vaddr; 522 let Inst{47-40} = vdata; 523 let Inst{52-48} = srsrc{6-2}; 524 let Inst{57-53} = ssamp{6-2}; 525} 526 527class FLATe<bits<7> op> : Enc64 { 528 bits<8> addr; 529 bits<8> data; 530 bits<8> vdst; 531 bits<1> slc; 532 bits<1> glc; 533 bits<1> tfe; 534 535 // 15-0 is reserved. 536 let Inst{16} = glc; 537 let Inst{17} = slc; 538 let Inst{24-18} = op; 539 let Inst{31-26} = 0x37; // Encoding. 540 let Inst{39-32} = addr; 541 let Inst{47-40} = data; 542 // 54-48 is reserved. 543 let Inst{55} = tfe; 544 let Inst{63-56} = vdst; 545} 546 547class EXPe : Enc64 { 548 bits<4> en; 549 bits<6> tgt; 550 bits<1> compr; 551 bits<1> done; 552 bits<1> vm; 553 bits<8> vsrc0; 554 bits<8> vsrc1; 555 bits<8> vsrc2; 556 bits<8> vsrc3; 557 558 let Inst{3-0} = en; 559 let Inst{9-4} = tgt; 560 let Inst{10} = compr; 561 let Inst{11} = done; 562 let Inst{12} = vm; 563 let Inst{31-26} = 0x3e; 564 let Inst{39-32} = vsrc0; 565 let Inst{47-40} = vsrc1; 566 let Inst{55-48} = vsrc2; 567 let Inst{63-56} = vsrc3; 568} 569 570let Uses = [EXEC] in { 571 572class VOP1 <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> : 573 VOP1Common <outs, ins, asm, pattern>, 574 VOP1e<op> { 575 let isCodeGenOnly = 0; 576} 577 578class VOP2 <bits<6> op, dag outs, dag ins, string asm, list<dag> pattern> : 579 VOP2Common <outs, ins, asm, pattern>, VOP2e<op> { 580 let isCodeGenOnly = 0; 581} 582 583class VOPC <bits<8> op, dag ins, string asm, list<dag> pattern> : 584 VOPCCommon <ins, asm, pattern>, VOPCe <op>; 585 586class VINTRPCommon <dag outs, dag ins, string asm, list<dag> pattern> : 587 InstSI <outs, ins, asm, pattern> { 588 let mayLoad = 1; 589 let mayStore = 0; 590 let hasSideEffects = 0; 591} 592 593} // End Uses = [EXEC] 594 595//===----------------------------------------------------------------------===// 596// Vector I/O operations 597//===----------------------------------------------------------------------===// 598 599let Uses = [EXEC] in { 600 601class DS <dag outs, dag ins, string asm, list<dag> pattern> : 602 InstSI <outs, ins, asm, pattern> { 603 604 let LGKM_CNT = 1; 605 let DS = 1; 606 let UseNamedOperandTable = 1; 607 let DisableEncoding = "$m0"; 608 609 // Most instruction load and store data, so set this as the default. 610 let mayLoad = 1; 611 let mayStore = 1; 612 613 let hasSideEffects = 0; 614 let AsmMatchConverter = "cvtDS"; 615 let SchedRW = [WriteLDS]; 616} 617 618class MUBUF <dag outs, dag ins, string asm, list<dag> pattern> : 619 InstSI<outs, ins, asm, pattern> { 620 621 let VM_CNT = 1; 622 let EXP_CNT = 1; 623 let MUBUF = 1; 624 625 let hasSideEffects = 0; 626 let UseNamedOperandTable = 1; 627 let AsmMatchConverter = "cvtMubuf"; 628 let SchedRW = [WriteVMEM]; 629} 630 631class MTBUF <dag outs, dag ins, string asm, list<dag> pattern> : 632 InstSI<outs, ins, asm, pattern> { 633 634 let VM_CNT = 1; 635 let EXP_CNT = 1; 636 let MTBUF = 1; 637 638 let hasSideEffects = 0; 639 let UseNamedOperandTable = 1; 640 let SchedRW = [WriteVMEM]; 641} 642 643class FLAT <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> : 644 InstSI<outs, ins, asm, pattern>, FLATe <op> { 645 let FLAT = 1; 646 // Internally, FLAT instruction are executed as both an LDS and a 647 // Buffer instruction; so, they increment both VM_CNT and LGKM_CNT 648 // and are not considered done until both have been decremented. 649 let VM_CNT = 1; 650 let LGKM_CNT = 1; 651 652 let Uses = [EXEC, FLAT_SCR]; // M0 653 654 let UseNamedOperandTable = 1; 655 let hasSideEffects = 0; 656} 657 658class MIMG <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> : 659 InstSI <outs, ins, asm, pattern>, MIMGe <op> { 660 661 let VM_CNT = 1; 662 let EXP_CNT = 1; 663 let MIMG = 1; 664 665 let hasSideEffects = 0; // XXX ???? 666} 667 668 669} // End Uses = [EXEC] 670