1//===-- X86InstrControl.td - Control Flow Instructions -----*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the X86 jump, return, call, and related instructions. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Control Flow Instructions. 16// 17 18// Return instructions. 19// 20// The X86retflag return instructions are variadic because we may add ST0 and 21// ST1 arguments when returning values on the x87 stack. 22let isTerminator = 1, isReturn = 1, isBarrier = 1, 23 hasCtrlDep = 1, FPForm = SpecialFP, SchedRW = [WriteJumpLd] in { 24 def RETL : I <0xC3, RawFrm, (outs), (ins variable_ops), 25 "ret{l}", [(X86retflag 0)], IIC_RET>, OpSize32, 26 Requires<[Not64BitMode]>; 27 def RETQ : I <0xC3, RawFrm, (outs), (ins variable_ops), 28 "ret{q}", [(X86retflag 0)], IIC_RET>, OpSize32, 29 Requires<[In64BitMode]>; 30 def RETW : I <0xC3, RawFrm, (outs), (ins), 31 "ret{w}", 32 [], IIC_RET>, OpSize16; 33 def RETIL : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops), 34 "ret{l}\t$amt", 35 [(X86retflag timm:$amt)], IIC_RET_IMM>, OpSize32, 36 Requires<[Not64BitMode]>; 37 def RETIQ : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops), 38 "ret{q}\t$amt", 39 [(X86retflag timm:$amt)], IIC_RET_IMM>, OpSize32, 40 Requires<[In64BitMode]>; 41 def RETIW : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt), 42 "ret{w}\t$amt", 43 [], IIC_RET_IMM>, OpSize16; 44 def LRETL : I <0xCB, RawFrm, (outs), (ins), 45 "{l}ret{l|f}", [], IIC_RET>, OpSize32; 46 def LRETQ : RI <0xCB, RawFrm, (outs), (ins), 47 "{l}ret{|f}q", [], IIC_RET>, Requires<[In64BitMode]>; 48 def LRETW : I <0xCB, RawFrm, (outs), (ins), 49 "{l}ret{w|f}", [], IIC_RET>, OpSize16; 50 def LRETIL : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt), 51 "{l}ret{l|f}\t$amt", [], IIC_RET>, OpSize32; 52 def LRETIQ : RIi16<0xCA, RawFrm, (outs), (ins i16imm:$amt), 53 "{l}ret{|f}q\t$amt", [], IIC_RET>, Requires<[In64BitMode]>; 54 def LRETIW : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt), 55 "{l}ret{w|f}\t$amt", [], IIC_RET>, OpSize16; 56} 57 58// Unconditional branches. 59let isBarrier = 1, isBranch = 1, isTerminator = 1, SchedRW = [WriteJump] in { 60 def JMP_1 : Ii8PCRel<0xEB, RawFrm, (outs), (ins brtarget8:$dst), 61 "jmp\t$dst", [(br bb:$dst)], IIC_JMP_REL>; 62 let hasSideEffects = 0, isCodeGenOnly = 1, ForceDisassemble = 1 in { 63 def JMP_2 : Ii16PCRel<0xE9, RawFrm, (outs), (ins brtarget16:$dst), 64 "jmp\t$dst", [], IIC_JMP_REL>, OpSize16; 65 def JMP_4 : Ii32PCRel<0xE9, RawFrm, (outs), (ins brtarget32:$dst), 66 "jmp\t$dst", [], IIC_JMP_REL>, OpSize32; 67 } 68} 69 70// Conditional Branches. 71let isBranch = 1, isTerminator = 1, Uses = [EFLAGS], SchedRW = [WriteJump] in { 72 multiclass ICBr<bits<8> opc1, bits<8> opc4, string asm, PatFrag Cond> { 73 def _1 : Ii8PCRel <opc1, RawFrm, (outs), (ins brtarget8:$dst), asm, 74 [(X86brcond bb:$dst, Cond, EFLAGS)], IIC_Jcc>; 75 let hasSideEffects = 0, isCodeGenOnly = 1, ForceDisassemble = 1 in { 76 def _2 : Ii16PCRel<opc4, RawFrm, (outs), (ins brtarget16:$dst), asm, 77 [], IIC_Jcc>, OpSize16, TB; 78 def _4 : Ii32PCRel<opc4, RawFrm, (outs), (ins brtarget32:$dst), asm, 79 [], IIC_Jcc>, TB, OpSize32; 80 } 81 } 82} 83 84defm JO : ICBr<0x70, 0x80, "jo\t$dst" , X86_COND_O>; 85defm JNO : ICBr<0x71, 0x81, "jno\t$dst", X86_COND_NO>; 86defm JB : ICBr<0x72, 0x82, "jb\t$dst" , X86_COND_B>; 87defm JAE : ICBr<0x73, 0x83, "jae\t$dst", X86_COND_AE>; 88defm JE : ICBr<0x74, 0x84, "je\t$dst" , X86_COND_E>; 89defm JNE : ICBr<0x75, 0x85, "jne\t$dst", X86_COND_NE>; 90defm JBE : ICBr<0x76, 0x86, "jbe\t$dst", X86_COND_BE>; 91defm JA : ICBr<0x77, 0x87, "ja\t$dst" , X86_COND_A>; 92defm JS : ICBr<0x78, 0x88, "js\t$dst" , X86_COND_S>; 93defm JNS : ICBr<0x79, 0x89, "jns\t$dst", X86_COND_NS>; 94defm JP : ICBr<0x7A, 0x8A, "jp\t$dst" , X86_COND_P>; 95defm JNP : ICBr<0x7B, 0x8B, "jnp\t$dst", X86_COND_NP>; 96defm JL : ICBr<0x7C, 0x8C, "jl\t$dst" , X86_COND_L>; 97defm JGE : ICBr<0x7D, 0x8D, "jge\t$dst", X86_COND_GE>; 98defm JLE : ICBr<0x7E, 0x8E, "jle\t$dst", X86_COND_LE>; 99defm JG : ICBr<0x7F, 0x8F, "jg\t$dst" , X86_COND_G>; 100 101// jcx/jecx/jrcx instructions. 102let isBranch = 1, isTerminator = 1, hasSideEffects = 0, SchedRW = [WriteJump] in { 103 // These are the 32-bit versions of this instruction for the asmparser. In 104 // 32-bit mode, the address size prefix is jcxz and the unprefixed version is 105 // jecxz. 106 let Uses = [CX] in 107 def JCXZ : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst), 108 "jcxz\t$dst", [], IIC_JCXZ>, AdSize16; 109 let Uses = [ECX] in 110 def JECXZ : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst), 111 "jecxz\t$dst", [], IIC_JCXZ>, AdSize32; 112 113 let Uses = [RCX] in 114 def JRCXZ : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst), 115 "jrcxz\t$dst", [], IIC_JCXZ>, AdSize64; 116} 117 118// Indirect branches 119let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { 120 def JMP16r : I<0xFF, MRM4r, (outs), (ins GR16:$dst), "jmp{w}\t{*}$dst", 121 [(brind GR16:$dst)], IIC_JMP_REG>, Requires<[Not64BitMode]>, 122 OpSize16, Sched<[WriteJump]>; 123 def JMP16m : I<0xFF, MRM4m, (outs), (ins i16mem:$dst), "jmp{w}\t{*}$dst", 124 [(brind (loadi16 addr:$dst))], IIC_JMP_MEM>, 125 Requires<[Not64BitMode]>, OpSize16, Sched<[WriteJumpLd]>; 126 127 def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst", 128 [(brind GR32:$dst)], IIC_JMP_REG>, Requires<[Not64BitMode]>, 129 OpSize32, Sched<[WriteJump]>; 130 def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst", 131 [(brind (loadi32 addr:$dst))], IIC_JMP_MEM>, 132 Requires<[Not64BitMode]>, OpSize32, Sched<[WriteJumpLd]>; 133 134 def JMP64r : I<0xFF, MRM4r, (outs), (ins GR64:$dst), "jmp{q}\t{*}$dst", 135 [(brind GR64:$dst)], IIC_JMP_REG>, Requires<[In64BitMode]>, 136 Sched<[WriteJump]>; 137 def JMP64m : I<0xFF, MRM4m, (outs), (ins i64mem:$dst), "jmp{q}\t{*}$dst", 138 [(brind (loadi64 addr:$dst))], IIC_JMP_MEM>, 139 Requires<[In64BitMode]>, Sched<[WriteJumpLd]>; 140 141 let Predicates = [Not64BitMode] in { 142 def FARJMP16i : Iseg16<0xEA, RawFrmImm16, (outs), 143 (ins i16imm:$off, i16imm:$seg), 144 "ljmp{w}\t$seg, $off", [], 145 IIC_JMP_FAR_PTR>, OpSize16, Sched<[WriteJump]>; 146 def FARJMP32i : Iseg32<0xEA, RawFrmImm16, (outs), 147 (ins i32imm:$off, i16imm:$seg), 148 "ljmp{l}\t$seg, $off", [], 149 IIC_JMP_FAR_PTR>, OpSize32, Sched<[WriteJump]>; 150 } 151 def FARJMP64 : RI<0xFF, MRM5m, (outs), (ins opaque80mem:$dst), 152 "ljmp{q}\t{*}$dst", [], IIC_JMP_FAR_MEM>, 153 Sched<[WriteJump]>; 154 155 def FARJMP16m : I<0xFF, MRM5m, (outs), (ins opaque32mem:$dst), 156 "ljmp{w}\t{*}$dst", [], IIC_JMP_FAR_MEM>, OpSize16, 157 Sched<[WriteJumpLd]>; 158 def FARJMP32m : I<0xFF, MRM5m, (outs), (ins opaque48mem:$dst), 159 "ljmp{l}\t{*}$dst", [], IIC_JMP_FAR_MEM>, OpSize32, 160 Sched<[WriteJumpLd]>; 161} 162 163 164// Loop instructions 165let SchedRW = [WriteJump] in { 166def LOOP : Ii8PCRel<0xE2, RawFrm, (outs), (ins brtarget8:$dst), "loop\t$dst", [], IIC_LOOP>; 167def LOOPE : Ii8PCRel<0xE1, RawFrm, (outs), (ins brtarget8:$dst), "loope\t$dst", [], IIC_LOOPE>; 168def LOOPNE : Ii8PCRel<0xE0, RawFrm, (outs), (ins brtarget8:$dst), "loopne\t$dst", [], IIC_LOOPNE>; 169} 170 171//===----------------------------------------------------------------------===// 172// Call Instructions... 173// 174let isCall = 1 in 175 // All calls clobber the non-callee saved registers. ESP is marked as 176 // a use to prevent stack-pointer assignments that appear immediately 177 // before calls from potentially appearing dead. Uses for argument 178 // registers are added manually. 179 let Uses = [ESP] in { 180 def CALLpcrel32 : Ii32PCRel<0xE8, RawFrm, 181 (outs), (ins i32imm_pcrel:$dst), 182 "call{l}\t$dst", [], IIC_CALL_RI>, OpSize32, 183 Requires<[Not64BitMode]>, Sched<[WriteJump]>; 184 let hasSideEffects = 0 in 185 def CALLpcrel16 : Ii16PCRel<0xE8, RawFrm, 186 (outs), (ins i16imm_pcrel:$dst), 187 "call{w}\t$dst", [], IIC_CALL_RI>, OpSize16, 188 Sched<[WriteJump]>; 189 def CALL16r : I<0xFF, MRM2r, (outs), (ins GR16:$dst), 190 "call{w}\t{*}$dst", [(X86call GR16:$dst)], IIC_CALL_RI>, 191 OpSize16, Requires<[Not64BitMode]>, Sched<[WriteJump]>; 192 def CALL16m : I<0xFF, MRM2m, (outs), (ins i16mem:$dst), 193 "call{w}\t{*}$dst", [(X86call (loadi16 addr:$dst))], 194 IIC_CALL_MEM>, OpSize16, 195 Requires<[Not64BitMode,FavorMemIndirectCall]>, 196 Sched<[WriteJumpLd]>; 197 def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst), 198 "call{l}\t{*}$dst", [(X86call GR32:$dst)], IIC_CALL_RI>, 199 OpSize32, Requires<[Not64BitMode]>, Sched<[WriteJump]>; 200 def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst), 201 "call{l}\t{*}$dst", [(X86call (loadi32 addr:$dst))], 202 IIC_CALL_MEM>, OpSize32, 203 Requires<[Not64BitMode,FavorMemIndirectCall]>, 204 Sched<[WriteJumpLd]>; 205 206 let Predicates = [Not64BitMode] in { 207 def FARCALL16i : Iseg16<0x9A, RawFrmImm16, (outs), 208 (ins i16imm:$off, i16imm:$seg), 209 "lcall{w}\t$seg, $off", [], 210 IIC_CALL_FAR_PTR>, OpSize16, Sched<[WriteJump]>; 211 def FARCALL32i : Iseg32<0x9A, RawFrmImm16, (outs), 212 (ins i32imm:$off, i16imm:$seg), 213 "lcall{l}\t$seg, $off", [], 214 IIC_CALL_FAR_PTR>, OpSize32, Sched<[WriteJump]>; 215 } 216 217 def FARCALL16m : I<0xFF, MRM3m, (outs), (ins opaque32mem:$dst), 218 "lcall{w}\t{*}$dst", [], IIC_CALL_FAR_MEM>, OpSize16, 219 Sched<[WriteJumpLd]>; 220 def FARCALL32m : I<0xFF, MRM3m, (outs), (ins opaque48mem:$dst), 221 "lcall{l}\t{*}$dst", [], IIC_CALL_FAR_MEM>, OpSize32, 222 Sched<[WriteJumpLd]>; 223 } 224 225 226// Tail call stuff. 227 228let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, 229 isCodeGenOnly = 1, SchedRW = [WriteJumpLd] in 230 let Uses = [ESP] in { 231 def TCRETURNdi : PseudoI<(outs), 232 (ins i32imm_pcrel:$dst, i32imm:$offset), []>; 233 def TCRETURNri : PseudoI<(outs), 234 (ins ptr_rc_tailcall:$dst, i32imm:$offset), []>; 235 let mayLoad = 1 in 236 def TCRETURNmi : PseudoI<(outs), 237 (ins i32mem_TC:$dst, i32imm:$offset), []>; 238 239 // FIXME: The should be pseudo instructions that are lowered when going to 240 // mcinst. 241 def TAILJMPd : Ii32PCRel<0xE9, RawFrm, (outs), 242 (ins i32imm_pcrel:$dst), 243 "jmp\t$dst", 244 [], IIC_JMP_REL>; 245 def TAILJMPr : I<0xFF, MRM4r, (outs), (ins ptr_rc_tailcall:$dst), 246 "", [], IIC_JMP_REG>; // FIXME: Remove encoding when JIT is dead. 247 let mayLoad = 1 in 248 def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem_TC:$dst), 249 "jmp{l}\t{*}$dst", [], IIC_JMP_MEM>; 250} 251 252 253//===----------------------------------------------------------------------===// 254// Call Instructions... 255// 256 257// RSP is marked as a use to prevent stack-pointer assignments that appear 258// immediately before calls from potentially appearing dead. Uses for argument 259// registers are added manually. 260let isCall = 1, Uses = [RSP], SchedRW = [WriteJump] in { 261 // NOTE: this pattern doesn't match "X86call imm", because we do not know 262 // that the offset between an arbitrary immediate and the call will fit in 263 // the 32-bit pcrel field that we have. 264 def CALL64pcrel32 : Ii32PCRel<0xE8, RawFrm, 265 (outs), (ins i64i32imm_pcrel:$dst), 266 "call{q}\t$dst", [], IIC_CALL_RI>, OpSize32, 267 Requires<[In64BitMode]>; 268 def CALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst), 269 "call{q}\t{*}$dst", [(X86call GR64:$dst)], 270 IIC_CALL_RI>, 271 Requires<[In64BitMode]>; 272 def CALL64m : I<0xFF, MRM2m, (outs), (ins i64mem:$dst), 273 "call{q}\t{*}$dst", [(X86call (loadi64 addr:$dst))], 274 IIC_CALL_MEM>, 275 Requires<[In64BitMode,FavorMemIndirectCall]>; 276 277 def FARCALL64 : RI<0xFF, MRM3m, (outs), (ins opaque80mem:$dst), 278 "lcall{q}\t{*}$dst", [], IIC_CALL_FAR_MEM>; 279} 280 281let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, 282 isCodeGenOnly = 1, Uses = [RSP], usesCustomInserter = 1, 283 SchedRW = [WriteJump] in { 284 def TCRETURNdi64 : PseudoI<(outs), 285 (ins i64i32imm_pcrel:$dst, i32imm:$offset), 286 []>; 287 def TCRETURNri64 : PseudoI<(outs), 288 (ins ptr_rc_tailcall:$dst, i32imm:$offset), []>; 289 let mayLoad = 1 in 290 def TCRETURNmi64 : PseudoI<(outs), 291 (ins i64mem_TC:$dst, i32imm:$offset), []>; 292 293 def TAILJMPd64 : Ii32PCRel<0xE9, RawFrm, (outs), (ins i64i32imm_pcrel:$dst), 294 "jmp\t$dst", [], IIC_JMP_REL>; 295 def TAILJMPr64 : I<0xFF, MRM4r, (outs), (ins ptr_rc_tailcall:$dst), 296 "jmp{q}\t{*}$dst", [], IIC_JMP_MEM>; 297 298 let mayLoad = 1 in 299 def TAILJMPm64 : I<0xFF, MRM4m, (outs), (ins i64mem_TC:$dst), 300 "jmp{q}\t{*}$dst", [], IIC_JMP_MEM>; 301 302 // Win64 wants jumps leaving the function to have a REX_W prefix. 303 let hasREX_WPrefix = 1 in { 304 def TAILJMPd64_REX : Ii32PCRel<0xE9, RawFrm, (outs), 305 (ins i64i32imm_pcrel:$dst), 306 "rex64 jmp\t$dst", [], IIC_JMP_REL>; 307 def TAILJMPr64_REX : I<0xFF, MRM4r, (outs), (ins ptr_rc_tailcall:$dst), 308 "rex64 jmp{q}\t{*}$dst", [], IIC_JMP_MEM>; 309 310 let mayLoad = 1 in 311 def TAILJMPm64_REX : I<0xFF, MRM4m, (outs), (ins i64mem_TC:$dst), 312 "rex64 jmp{q}\t{*}$dst", [], IIC_JMP_MEM>; 313 } 314} 315